On Thu, Mar 21, 2024 at 4:49 PM Philippe Mathieu-Daudé <phi...@linaro.org>
wrote:
> MicroBlaze MMU API is exposed in "mmu.h". In order to avoid
> name clashing with other targets, prefix the API with 'mb_'.
>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
> ---
> target/microblaze/mmu.h | 10 +++++-----
> target/microblaze/cpu.c | 2 +-
> target/microblaze/helper.c | 4 ++--
> target/microblaze/mmu.c | 14 +++++++-------
> target/microblaze/op_helper.c | 4 ++--
> 5 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
> index 1068bd2d52..5b51e0a9c6 100644
> --- a/target/microblaze/mmu.h
> +++ b/target/microblaze/mmu.h
> @@ -85,10 +85,10 @@ typedef struct {
> } err;
> } MicroBlazeMMULookup;
>
> -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> - target_ulong vaddr, MMUAccessType rw, int
> mmu_idx);
> -uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
> -void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
> -void mmu_init(MicroBlazeMMU *mmu);
> +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> + target_ulong vaddr, MMUAccessType rw, int
> mmu_idx);
> +uint32_t mb_mmu_read(CPUMBState *env, bool ea, uint32_t rn);
> +void mb_mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
> +void mb_mmu_init(MicroBlazeMMU *mmu);
>
> #endif
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 96c2b71f7f..59bfb5c45d 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -205,7 +205,7 @@ static void mb_cpu_reset_hold(Object *obj)
> mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
> #else
> mb_cpu_write_msr(env, 0);
> - mmu_init(&env->mmu);
> + mb_mmu_init(&env->mmu);
> #endif
> }
>
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index d25c9eb4d3..961687bae7 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -57,7 +57,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> return true;
> }
>
> - hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
> + hit = mb_mmu_translate(cpu, &lu, address, access_type, mmu_idx);
> if (likely(hit)) {
> uint32_t vaddr = address & TARGET_PAGE_MASK;
> uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
> @@ -238,7 +238,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs,
> vaddr addr,
> attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD);
>
> if (mmu_idx != MMU_NOMMU_IDX) {
> - hit = mmu_translate(cpu, &lu, addr, 0, 0);
> + hit = mb_mmu_translate(cpu, &lu, addr, 0, 0);
> if (hit) {
> vaddr = addr & TARGET_PAGE_MASK;
> paddr = lu.paddr + vaddr - lu.vaddr;
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index 234006634e..5fb8ee8418 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -74,8 +74,8 @@ static void mmu_change_pid(CPUMBState *env, unsigned int
> newpid)
> }
>
> /* rw - 0 = read, 1 = write, 2 = fetch. */
> -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> - target_ulong vaddr, MMUAccessType rw, int
> mmu_idx)
> +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> + target_ulong vaddr, MMUAccessType rw, int
> mmu_idx)
> {
> MicroBlazeMMU *mmu = &cpu->env.mmu;
> unsigned int i, hit = 0;
> @@ -175,7 +175,7 @@ done:
> }
>
> /* Writes/reads to the MMU's special regs end up here. */
> -uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
> +uint32_t mb_mmu_read(CPUMBState *env, bool ext, uint32_t rn)
> {
> MicroBlazeCPU *cpu = env_archcpu(env);
> unsigned int i;
> @@ -228,7 +228,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t
> rn)
> return r;
> }
>
> -void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
> +void mb_mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
> {
> MicroBlazeCPU *cpu = env_archcpu(env);
> uint64_t tmp64;
> @@ -304,8 +304,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn,
> uint32_t v)
> return;
> }
>
> - hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
> - 0, cpu_mmu_index(env_cpu(env), false));
> + hit = mb_mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
> + 0, cpu_mmu_index(env_cpu(env), false));
> if (hit) {
> env->mmu.regs[MMU_R_TLBX] = lu.idx;
> } else {
> @@ -319,7 +319,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn,
> uint32_t v)
> }
> }
>
> -void mmu_init(MicroBlazeMMU *mmu)
> +void mb_mmu_init(MicroBlazeMMU *mmu)
> {
> int i;
> for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f6378030b7..58475a3af5 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -386,12 +386,12 @@ void helper_stackprot(CPUMBState *env, target_ulong
> addr)
> /* Writes/reads to the MMU's special regs end up here. */
> uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> {
> - return mmu_read(env, ext, rn);
> + return mb_mmu_read(env, ext, rn);
> }
>
> void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn,
> uint32_t v)
> {
> - mmu_write(env, ext, rn, v);
> + mb_mmu_write(env, ext, rn, v);
> }
>
> void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> --
> 2.41.0
>
>
