On Tue, Apr 30, 2024 at 5:29 AM Atish Patra <ati...@rivosinc.com> wrote: > > This series contains few miscallenous fixes related to hpmcounters > and related code. The first patch fixes an issue with cycle/instret > counters overcouting while the remaining two are more for specification > compliance. > > Signed-off-by: Atish Patra <ati...@rivosinc.com> > --- > Atish Patra (3): > target/riscv: Save counter values during countinhibit update > target/riscv: Enforce WARL behavior for scounteren/hcounteren > target/riscv: Fix the predicate functions for mhpmeventhX CSRs
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 1 - > target/riscv/csr.c | 111 > ++++++++++++++++++++++++++++++------------------- > target/riscv/machine.c | 1 - > 3 files changed, 68 insertions(+), 45 deletions(-) > --- > base-commit: 1642f979a71a5667a05070be2df82f48bd43ad7a > change-id: 20240428-countinhibit_fix-c6a1c11f4375 > -- > Regards, > Atish patra > >
