On Mon, May 13, 2024 at 11:29 PM Alistair Francis <alistai...@gmail.com> wrote: > > On Tue, Apr 30, 2024 at 5:29 AM Atish Patra <ati...@rivosinc.com> wrote: > > > > This series contains few miscallenous fixes related to hpmcounters > > and related code. The first patch fixes an issue with cycle/instret > > counters overcouting while the remaining two are more for specification > > compliance. > > > > Signed-off-by: Atish Patra <ati...@rivosinc.com> > > --- > > Atish Patra (3): > > target/riscv: Save counter values during countinhibit update > > target/riscv: Enforce WARL behavior for scounteren/hcounteren > > target/riscv: Fix the predicate functions for mhpmeventhX CSRs > > Thanks! > > Applied to riscv-to-apply.next >
Hi Alistair, Thanks for your review. But the patch 1 had some comments about vmstate which needs updating. We also found a few more fixes that I was planning to include in v2. I can send a separate fixes series on top riscv-to-apply.next or this series can be dropped for the time being. You can queue it v2 later. Let me know what you prefer. > Alistair > > > > > target/riscv/cpu.h | 1 - > > target/riscv/csr.c | 111 > > ++++++++++++++++++++++++++++++------------------- > > target/riscv/machine.c | 1 - > > 3 files changed, 68 insertions(+), 45 deletions(-) > > --- > > base-commit: 1642f979a71a5667a05070be2df82f48bd43ad7a > > change-id: 20240428-countinhibit_fix-c6a1c11f4375 > > -- > > Regards, > > Atish patra > > > >