On 5/28/24 12:35, Aditya Gupta wrote:
Add sPAPR CPU Core definition for Power11

Cc: David Gibson <da...@gibson.dropbear.id.au> (reviewer:sPAPR (pseries))
Cc: Harsh Prateek Bora <hars...@linux.ibm.com> (reviewer:sPAPR (pseries))
Cc: Cédric Le Goater <c...@kaod.org>
Cc: Daniel Henrique Barboza <danielhb...@gmail.com>
Cc: Frédéric Barrat <fbar...@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mah...@linux.ibm.com>
Cc: Madhavan Srinivasan <ma...@linux.ibm.com>
Cc: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Aditya Gupta <adit...@linux.ibm.com>
---
  docs/system/ppc/pseries.rst | 6 +++---
  hw/ppc/spapr_cpu_core.c     | 1 +
  2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -15,9 +15,9 @@ Supported devices
  =================
* Multi processor support for many Power processors generations: POWER7,
-   POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
-   but its state is unknown.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
+   POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
+   exists, but its state is unknown.
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)

I think it would look more cleaner to rephrase as below:

 * Multi processor support for many Power processors generations:
   - POWER7, POWER7+
   - POWER8, POWER8NVL
   - POWER9
   - Power10
   - Power11.
   - Support for POWER5+ exists, but its state is unknown.
 * Interrupt Controller
    - XICS (POWER8)
    - XIVE (Supported by below:)
        - POWER9
        - Power10
        - Power11

So, that every next platform just need to add one line for itself.

With that,
Reviewed-by: Harsh Prateek Bora <hars...@linux.ibm.com>

Thanks
Harsh
   * vPHB PCIe Host bridge.
   * vscsi and vnet devices, compatible with the same devices available on a
     PowerVM hypervisor with VIOS managing LPARs.
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index e7c9edd033c8..62416b7e0a7e 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
      DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
      DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
      DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
+    DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"),
  #ifdef CONFIG_KVM
      DEFINE_SPAPR_CPU_CORE_TYPE("host"),
  #endif

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