Handle MIPS DSP instructions in target-mips/translate.c.
Signed-off-by: Jia Liu <pro...@gmail.com>
---
target-mips/translate.c | 943 +++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 943 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c698e78..0b31b46 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -359,6 +359,224 @@ enum {
OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
};
+#define MASK_ABSQ_S_PH(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
+};
+
+/* MIPS DSPR2 */
+enum {
+ OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
+};
+
+#define MASK_ADDU_QB(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
+ OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
+};
+
+/* MIPS DSPR2 */
+enum {
+ OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
+};
+
+#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
+#define MASK_ADDUH_QB(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSPR2 */
+enum {
+ OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
+ OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
+};
+
+#define OPC_MUL_PH_DSP OPC_ADDUH_QB_DSP
+/* #define MASK_MUL_PH(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) */
+/* MIPS DSPR2 */
+enum {
+ OPC_MULQ_RS_W = (0x17 << 6) | OPC_MUL_PH_DSP,
+ OPC_MULQ_S_W = (0x16 << 6) | OPC_MUL_PH_DSP,
+};
+
+#define MASK_APPEND(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSPR2 */
+enum {
+ OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
+ OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
+ OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
+};
+
+#define MASK_CMPU_EQ_QB(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
+};
+
+/* MIPS DSPR2 */
+enum {
+ OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
+};
+
+#define MASK_DPA_W_PH(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
+};
+
+/* MIPS DSPR2 */
+enum{
+ OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
+};
+
+#define MASK_EXTR_W(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
+ OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
+ OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
+ OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
+ OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
+ OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
+ OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
+};
+
+#define MASK_INSV(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
+};
+
+
+#define MASK_SHLL_QB(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
+/* MIPS DSP */
+enum {
+ OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
+};
+
+/* MIPS DSPR2 */
+enum {
+ OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -12081,10 +12299,735 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
break;
case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
+ /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
+ * the same mask and op1. */
+ if (op1 == OPC_MULT_G_2E) {
+ int is_mult_g_2e = 0;
+ op2 = MASK_ADDUH_QB(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSPR2 */
+ case OPC_ADDQH_PH:
+ gen_helper_addqh_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_R_PH:
+ gen_helper_addqh_r_ph(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_W:
+ gen_helper_addqh_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_R_W:
+ gen_helper_addqh_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_ADDUH_QB:
+ gen_helper_adduh_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDUH_R_QB:
+ gen_helper_adduh_r_qb(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MUL_PH:
+ gen_helper_mul_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MUL_S_PH:
+ gen_helper_mul_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_PH:
+ gen_helper_subqh_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_R_PH:
+ gen_helper_subqh_r_ph(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_W:
+ gen_helper_subqh_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_R_W:
+ gen_helper_subqh_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SUBUH_QB:
+ gen_helper_subuh_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBUH_R_QB:
+ gen_helper_subuh_r_qb(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ /* OPC_MUL_PH_DSP */
+ /* MIPS DSPR2 */
+ case OPC_MULQ_RS_W:
+ gen_helper_mulq_rs_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_S_W:
+ gen_helper_mulq_s_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ default:
+ is_mult_g_2e = 1;
+ break;
+ }
+ if (is_mult_g_2e == 0)
+ break;
+ }
case OPC_MOD_G_2E ... OPC_MODU_G_2E:
check_insn(env, ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
+ /* MIPS DSP opcodes */
+ case OPC_ABSQ_S_PH_DSP:
+ op2 = MASK_ABSQ_S_PH(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_ABSQ_S_PH:
+ gen_helper_absq_s_ph(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_ABSQ_S_W:
+ gen_helper_absq_s_w(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_BITREV:
+ gen_helper_bitrev(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQ_W_PHL:
+ gen_helper_preceq_w_phl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQ_W_PHR:
+ gen_helper_preceq_w_phr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBL:
+ gen_helper_precequ_ph_qbl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBLA:
+ gen_helper_precequ_ph_qbla(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBR:
+ gen_helper_precequ_ph_qbr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBRA:
+ gen_helper_precequ_ph_qbra(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBL:
+ gen_helper_preceu_ph_qbl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBLA:
+ gen_helper_preceu_ph_qbla(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBR:
+ gen_helper_preceu_ph_qbr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBRA:
+ gen_helper_preceu_ph_qbra(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_REPL_PH:
+ {
+ TCGv temp_imm;
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ temp_imm = tcg_const_i32(imm);
+ gen_helper_repl_ph(cpu_gpr[rd], temp_imm);
+ tcg_temp_free(temp_imm);
+ break;
+ }
+ case OPC_REPL_QB:
+ {
+ TCGv temp_imm;
+ imm = (ctx->opcode >> 16) & 0xFF;
+ temp_imm = tcg_const_i32(imm);
+ gen_helper_repl_qb(cpu_gpr[rd], temp_imm);
+ tcg_temp_free(temp_imm);
+ break;
+ }
+ case OPC_REPLV_PH:
+ gen_helper_replv_ph(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_REPLV_QB:
+ gen_helper_replv_qb(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ /* MIPS DSPR2 */
+ case OPC_ABSQ_S_QB:
+ gen_helper_absq_s_qb(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ }
+ break;
+ case OPC_ADDU_QB_DSP:
+ op2 = MASK_ADDU_QB(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_ADDQ_PH:
+ gen_helper_addq_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQ_S_PH:
+ gen_helper_addq_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQ_S_W:
+ gen_helper_addq_s_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDSC:
+ gen_helper_addsc(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_QB:
+ gen_helper_addu_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_S_QB:
+ gen_helper_addu_s_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDWC:
+ gen_helper_addwc(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MODSUB:
+ gen_helper_modsub(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULEQ_S_W_PHL:
+ gen_helper_muleq_s_w_phl(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MULEQ_S_W_PHR:
+ gen_helper_muleq_s_w_phr(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MULEU_S_PH_QBL:
+ gen_helper_muleu_s_ph_qbl(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MULEU_S_PH_QBR:
+ gen_helper_muleu_s_ph_qbr(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_RS_PH:
+ gen_helper_mulq_rs_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_RADDU_W_QB:
+ gen_helper_raddu_w_qb(cpu_gpr[rd], cpu_gpr[rs]);
+ break;
+ case OPC_SUBQ_PH:
+ gen_helper_subq_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQ_S_PH:
+ gen_helper_subq_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQ_S_W:
+ gen_helper_subq_s_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_QB:
+ gen_helper_subu_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_S_QB:
+ gen_helper_subu_s_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ /* MIPS DSPR2 */
+ case OPC_ADDU_PH:
+ gen_helper_addu_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_S_PH:
+ gen_helper_addu_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_S_PH:
+ gen_helper_mulq_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_PH:
+ gen_helper_subu_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_S_PH:
+ gen_helper_subu_s_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ break;
+ case OPC_APPEND_DSP:
+ op2 = MASK_APPEND(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSPR2 */
+ case OPC_APPEND:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_append(cpu_gpr[rt], cpu_gpr[rt],
+ cpu_gpr[rs], temp_rd);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_BALIGN:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_balign(cpu_gpr[rt], cpu_gpr[rt],
+ cpu_gpr[rs], temp_rd);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_PREPEND:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_prepend(cpu_gpr[rt], temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ }
+ break;
+ case OPC_CMPU_EQ_QB_DSP:
+ op2 = MASK_CMPU_EQ_QB(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_CMP_EQ_PH:
+ gen_helper_cmp_eq_ph(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMP_LT_PH:
+ gen_helper_cmp_lt_ph(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMP_LE_PH:
+ gen_helper_cmp_le_ph(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPGU_EQ_QB:
+ gen_helper_cmpgu_eq_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPGU_LT_QB:
+ gen_helper_cmpgu_lt_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPGU_LE_QB:
+ gen_helper_cmpgu_le_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPU_EQ_QB:
+ gen_helper_cmpu_eq_qb(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPU_LT_QB:
+ gen_helper_cmpu_lt_qb(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPU_LE_QB:
+ gen_helper_cmpu_le_qb(cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PACKRL_PH:
+ gen_helper_packrl_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PICK_QB:
+ gen_helper_pick_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PICK_PH:
+ gen_helper_pick_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQ_QB_PH:
+ gen_helper_precrq_qb_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQ_PH_W:
+ gen_helper_precrq_ph_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQ_RS_PH_W:
+ gen_helper_precrq_rs_ph_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQU_S_QB_PH:
+ gen_helper_precrqu_s_qb_ph(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ /* MIPS DSPR2 */
+ case OPC_CMPGDU_EQ_QB:
+ gen_helper_cmpgdu_eq_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPGDU_LT_QB:
+ gen_helper_cmpgdu_lt_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_CMPGDU_LE_QB:
+ gen_helper_cmpgdu_le_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECR_QB_PH:
+ gen_helper_precr_qb_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECR_SRA_PH_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_precr_sra_ph_w(cpu_gpr[rt], temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_PRECR_SRA_R_PH_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_precr_sra_r_ph_w(cpu_gpr[rt], temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ }
+ break;
+ case OPC_DPA_W_PH_DSP:
+ op2 = MASK_DPA_W_PH(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_DPAQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaq_s_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQ_SA_L_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaq_sa_l_w(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAU_H_QBL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpau_h_qbl(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAU_H_QBR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpau_h_qbr(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsq_s_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQ_SA_L_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsq_sa_l_w(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSU_H_QBL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsu_h_qbl(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSU_H_QBR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsu_h_qbr(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_S_W_PHL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_s_w_phl(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_SA_W_PHL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_sa_w_phl(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_S_W_PHR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_s_w_phr(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_SA_W_PHR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_sa_w_phr(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MULSAQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_mulsaq_s_w_ph(temp_rd, cpu_gpr[rs],
cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ /* MIPS DSPR2 */
+ case OPC_DPA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpa_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQX_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaqx_s_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQX_SA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaqx_sa_w_ph(temp_rd, cpu_gpr[rs],
cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAX_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpax_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPS_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dps_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQX_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsqx_s_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQX_SA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsqx_sa_w_ph(temp_rd, cpu_gpr[rs],
cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSX_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsx_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MULSA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_mulsa_w_ph(temp_rd, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ }
+ break;
+ case OPC_EXTR_W_DSP:
+ op2 = MASK_EXTR_W(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_EXTP:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extp(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTPDP:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extpdp(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTPDPV:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extpdpv(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_EXTPV:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extpv(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_EXTR_S_H:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extr_s_h(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTR_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extr_w(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTR_R_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extr_r_w(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTR_RS_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ TCGv temp_rs = tcg_const_i32(rs);
+ gen_helper_extr_rs_w(cpu_gpr[rt], temp_rd, temp_rs);
+ tcg_temp_free(temp_rd);
+ tcg_temp_free(temp_rs);
+ break;
+ }
+ case OPC_EXTRV_S_H:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extrv_s_h(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_EXTRV_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extrv_w(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_EXTRV_R_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extrv_r_w(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_EXTRV_RS_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_extrv_rs_w(cpu_gpr[rt], temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MTHLIP:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_mthlip(temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_RDDSP:
+ {
+ TCGv temp_imm;
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ temp_imm = tcg_const_i32(imm);
+ gen_helper_rddsp(cpu_gpr[rd], temp_imm);
+ tcg_temp_free(temp_imm);
+ break;
+ }
+ case OPC_SHILO:
+ {
+ TCGv temp_imm;
+ TCGv temp_rd = tcg_const_i32(rd);
+ imm = (ctx->opcode >> 20) & 0x3F;
+ temp_imm = tcg_const_i32(imm);
+ gen_helper_shilo(temp_rd, temp_imm);
+ tcg_temp_free(temp_imm);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_SHILOV:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_shilov(temp_rd, cpu_gpr[rs]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_WRDSP:
+ {
+ TCGv temp_imm;
+ imm = (ctx->opcode >> 11) & 0x3FF;
+ temp_imm = tcg_const_i32(imm);
+ gen_helper_wrdsp(cpu_gpr[rs], temp_imm);
+ tcg_temp_free(temp_imm);
+ break;
+ }
+ }
+ break;
+ case OPC_INSV_DSP:
+ op2 = MASK_INSV(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_INSV:
+ {
+ TCGv temp_rt = tcg_const_i32(rt);
+ gen_helper_insv(temp_rt, cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rt);
+ break;
+ }
+ }
+ break;
+ case OPC_SHLL_QB_DSP:
+ {
+ TCGv temp_rs = tcg_const_i32(rs);
+ op2 = MASK_SHLL_QB(ctx->opcode);
+ switch (op2) {
+ /* MIPS DSP */
+ case OPC_SHLL_PH:
+ gen_helper_shll_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_S_PH:
+ gen_helper_shll_s_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_QB:
+ gen_helper_shll_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_S_W:
+ gen_helper_shll_s_w(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_PH:
+ gen_helper_shllv_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_S_PH:
+ gen_helper_shllv_s_ph(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_QB:
+ gen_helper_shllv_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_S_W:
+ gen_helper_shllv_s_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_PH:
+ gen_helper_shra_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_PH:
+ gen_helper_shra_r_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_W:
+ gen_helper_shra_r_w(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_PH:
+ gen_helper_shrav_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_PH:
+ gen_helper_shrav_r_ph(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_W:
+ gen_helper_shrav_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SHRL_QB:
+ gen_helper_shrl_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRLV_QB:
+ gen_helper_shrlv_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ /* MIPS DSPR2 */
+ case OPC_SHRA_QB:
+ gen_helper_shra_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_QB:
+ gen_helper_shra_r_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_QB:
+ gen_helper_shrav_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_QB:
+ gen_helper_shrav_r_qb(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SHRL_PH:
+ gen_helper_shrl_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRLV_PH:
+ gen_helper_shrlv_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ tcg_temp_free(temp_rs);
+ break;
+ }
case OPC_LX_DSP:
op2 = MASK_LX(ctx->opcode);
switch (op2) {
--
1.7.5.4
