>-----Original Message-----
>From: CLEMENT MATHIEU--DRIF <clement.mathieu--d...@eviden.com>
>Subject: [PATCH v3 1/3] intel_iommu: fix FRCD construction macro.
>
>From: Clément Mathieu--Drif <clement.mathieu--d...@eviden.com>
>
>The constant must be unsigned, otherwise the two's complement
>overrides the other fields when a PASID is present.
>
>Fixes: 1b2b12376c8a ("intel-iommu: PASID support")
>
>Signed-off-by: Clément Mathieu--Drif <clement.mathieu--d...@eviden.com>
>Reviewed-by: Yi Liu <yi.l....@intel.com>
>---
> hw/i386/intel_iommu_internal.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/i386/intel_iommu_internal.h
>b/hw/i386/intel_iommu_internal.h
>index f8cf99bddf..cbc4030031 100644
>--- a/hw/i386/intel_iommu_internal.h
>+++ b/hw/i386/intel_iommu_internal.h
>@@ -267,7 +267,7 @@
> /* For the low 64-bit of 128-bit */
> #define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
> #define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40)
>-#define VTD_FRCD_PP(val) (((val) & 0x1) << 31)
>+#define VTD_FRCD_PP(val) (((val) & 0x1ULL) << 31)
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
VTD_FRCD_PV and VTD_FRCD_PP are MACROs for high 64-bit.
By this chance, maybe we can move them under:
/* For the high 64-bit of 128-bit */
Thanks
Zhenzhong
> #define VTD_FRCD_IR_IDX(val) (((val) & 0xffffULL) << 48)
>
> /* DMA Remapping Fault Conditions */
>--
>2.45.2
