On Fri, Jul 12, 2024 at 8:33 AM Atish Patra <ati...@rivosinc.com> wrote: > > This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle > and > privilege mode filtering) [1]. It is based on Kevin's earlier work but > improves > it by actually implement privilege mode filtering by tracking the privilege > mode switches. This enables the privilege mode filtering for mhpmcounters as > well. However, Smcntrpmf/Sscofpmf must be enabled to leverage this. > > The series is also available at [2] as well. > > Changes in v8: > - Moved the config option to a separate patch at the end of the series. > - Fixed a comments recieved in v7 around setting INH bit based on available > priv modes. > - Updated the RB/AB tags. > - Link to v7: > https://lore.kernel.org/r/20240626-smcntrpmf_v7-v7-0-bb0f10af7...@rivosinc.com > > Changes from v6->v7: > 1. Fixed a compilation issue. > > Changes from v5->v6: > 1. Rebased on top of alister/riscv-to-apply.next (c50aabe132) and icount fix > patch[4] which may cause conflicts. > 2. Fixed a bug in pmf logic related to VS<->HS transition and same mode > recording. > 3. Merged assorted fixes PR as the changes are intertwined. [2] > 4. Fix counter inhibit CSR behavior. This change now start counters from both > mhpmcounter and mcountinhibit writes. Previously cycle/inst timer was > only started on mhpmcounterx write. > 5. Optimized the PMU timer setup code. > > Changes from v4->v5: > 1. Rebased on top of master(158a054c4d1a). > 2. Fixed a bug for VS<->HS transition. > > Changes from v3->v4: > 1. Fixed the ordering of the ISA extension names in isa_edata_arr. > 2. Added RB tags. > > Changes from v2->v3: > 1. Fixed the rebasing error in PATCH2. > 2. Added RB tags. > 3. Addressed other review comments. > > Changes from v1->v2: > 1. Implemented actual mode filtering for both icount and host ticks mode. > 1. Addressed comments in v1. > 2. Added Kevin's personal email address. > > [1] https://github.com/riscv/riscv-smcntrpmf > [2] https://github.com/atishp04/qemu/tree/b4/smcntrpmf_v7 > [3] > https://lore.kernel.org/all/20240429-countinhibit_fix-v1-0-802ec1e99...@rivosinc.com/ > [4] > https://lore.kernel.org/qemu-riscv/20240618112649.76683-1-cle...@rivosinc.com/ > > Cc: Rajnesh Kanwal <rkan...@rivosinc.com> > > Signed-off-by: Atish Patra <ati...@rivosinc.com> > --- > Atish Patra (7): > target/riscv: Fix the predicate functions for mhpmeventhX CSRs > target/riscv: Only set INH fields if priv mode is available > target/riscv: Implement privilege mode filtering for cycle/instret > target/riscv: Save counter values during countinhibit update > target/riscv: Enforce WARL behavior for scounteren/hcounteren > target/riscv: Do not setup pmu timer if OF is disabled > target/riscv: Expose the Smcntrpmf config > > Kaiwen Xue (3): > target/riscv: Add cycle & instret privilege mode filtering properties > target/riscv: Add cycle & instret privilege mode filtering definitions > target/riscv: Add cycle & instret privilege mode filtering support > > Rajnesh Kanwal (3): > target/riscv: Combine set_mode and set_virt functions. > target/riscv: Start counters from both mhpmcounter and mcountinhibit > target/riscv: More accurately model priv mode filtering. > > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 20 ++- > target/riscv/cpu_bits.h | 41 +++++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_helper.c | 66 +++---- > target/riscv/csr.c | 437 > +++++++++++++++++++++++++++++++++++++--------- > target/riscv/machine.c | 5 +- > target/riscv/op_helper.c | 17 +- > target/riscv/pmu.c | 181 +++++++++++++++++-- > target/riscv/pmu.h | 4 + > 10 files changed, 624 insertions(+), 150 deletions(-)
Thanks! Applied to riscv-to-apply.next Alistair > --- > base-commit: 842a3d79a0e37cd3d685c4728308fac0d9bfd0bb > change-id: 20240626-smcntrpmf_v7-3b275d1da117 > -- > Regards, > Atish patra > >
