Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in `lpad`. If they don't match, cpu raises a
sw check exception with tval = 2.
Signed-off-by: Deepak Gupta <de...@rivosinc.com>
Co-developed-by: Jim Shu <jim....@sifive.com>
Co-developed-by: Andy Chiu <andy.c...@sifive.com>
---
target/riscv/cpu_user.h | 1 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 6 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 51 +++++++++++++++++++++++++
target/riscv/op_helper.c | 32 ++++++++++++++++
5 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index 02afad608b..e6927ff847 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -15,5 +15,6 @@
#define xA6 16
#define xA7 17 /* syscall number for RVI ABI */
#define xT0 5 /* syscall number for RVE ABI */
+#define xT2 7
#endif
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 451261ce5a..ab55bbbf73 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -121,6 +121,10 @@ DEF_HELPER_2(cbo_clean_flush, void, env, tl)
DEF_HELPER_2(cbo_inval, void, env, tl)
DEF_HELPER_2(cbo_zero, void, env, tl)
+/* Forward CFI label checking */
+DEF_HELPER_2(cfi_jalr, void, env, int)
+DEF_HELPER_2(cfi_check_landing_pad, void, env, int)
+
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c45b8fa1d8..c963c59c8e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
%imm_z6 26:1 15:5
%imm_mop5 30:1 26:2 20:2
%imm_mop3 30:1 26:2
+%imm_cfi20 12:20
# Argument sets:
&empty
@@ -123,7 +124,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011
@sfence_vm
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
-auipc .................... ..... 0010111 @u
+{
+ lpad .................... 00000 0010111 %imm_cfi20
+ auipc .................... ..... 0010111 @u
+}
jal .................... ..... 1101111 @j
jalr ............ ..... 000 ..... 1100111 @i
beq ....... ..... ..... 000 ..... 1100011 @b
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 98e3806d5e..ee868c5fcb 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -36,6 +36,44 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
return true;
}
+static bool trans_lpad(DisasContext *ctx, arg_lpad *a)
+{
+ /* zicfilp only supported on 32bit and 64bit */
+ if (get_xl(ctx) != MXL_RV32 && get_xl(ctx) != MXL_RV64) {
+ return false;
+ }
+
+ /* forward cfi not enabled, return false */
+ if (!ctx->fcfi_enabled) {
+ return false;
+ }
+
+ /*
+ * If this is the first instruction of the TB, let the translator
+ * know the landing pad requirement was satisfied. No need to bother
+ * checking for CFI feature or enablement.
+ */
+
+ if (ctx->base.pc_next == ctx->base.pc_first) {
+ ctx->fcfi_lp_expected = false;
+ /* PC must be 4 byte aligned */
+ if (ctx->fcfi_enabled && ((ctx->base.pc_next) & 0x3)) {
+ /*
+ * misaligned, according to spec we should raise sw check exception
+ */
+ tcg_gen_st_tl(
+ tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
+ tcg_env, offsetof(CPURISCVState, sw_check_code));
+ generate_exception(ctx, RISCV_EXCP_SW_CHECK);
+ return true;
+ }
+ }
+
+ /* use helper to do label check */
+ gen_helper_cfi_check_landing_pad(tcg_env, tcg_constant_i32(a->imm_cfi20));
+ return true;
+}
+
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
TCGv target_pc = dest_gpr(ctx, a->rd);
@@ -75,6 +113,19 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
gen_set_gpr(ctx, a->rd, succ_pc);
tcg_gen_mov_tl(cpu_pc, target_pc);
+ if (ctx->cfg_ptr->ext_zicfilp) {
+ /*
+ * Rely on a helper to check the forward CFI enable for the
+ * current process mode. The alternatives would be (1) include
+ * "fcfi enabled" in the cflags or (2) maintain a "fcfi
+ * currently enabled" in tcg_env and emit TCG code to access
+ * and test it.
+ */
+ if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) {
+ gen_helper_cfi_jalr(tcg_env, tcg_constant_i32(LP_EXPECTED));
+ }
+ }
+
lookup_and_goto_ptr(ctx);
if (misaligned) {
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 488116cc2e..2d152f0a00 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -259,6 +259,38 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong
address)
/* We don't emulate the cache-hierarchy, so we're done. */
}
+void helper_cfi_jalr(CPURISCVState *env, int elp)
+{
+ /*
+ * The translation routine doesn't know if forward CFI is enabled
+ * in the current processor mode or not. It's not worth burning a
+ * cflags bit to encode this, or tracking the current-mode-fcfi
+ * enable in a dedicated member of 'env'. Just come out to a helper
+ * for jump/call on a core with CFI.
+ */
+ if (cpu_get_fcfien(env)) {
+ env->elp = elp;
+ }
+}
+
+void helper_cfi_check_landing_pad(CPURISCVState *env, int lbl)
+{
+ if ((env->elp == LP_EXPECTED) && cpu_get_fcfien(env)) {
+ /*
+ * Check for the 20bit label match. We already checked 4 byte
+ * alignment in tcg
+ * High 20bits (b31:12) in x7/t2 hold label. We need drop bits
+ * greater than 31 and then shift 12 right
+ */
+ if (lbl && (lbl != ((env->gpr[xT2] & 0xFFFFFFFF) >> 12))) {
+ env->sw_check_code = RISCV_EXCP_SW_CHECK_FCFI_TVAL;
+ riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC());
+ }
+
+ env->elp = NO_LP_EXPECTED;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
target_ulong helper_sret(CPURISCVState *env)
--
2.44.0
