Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case.
Signed-off-by: Jim Shu <jim....@sifive.com> Signed-off-by: Deepak Gupta <de...@rivosinc.com> --- target/riscv/insn_trans/trans_rvi.c.inc | 1 + target/riscv/op_helper.c | 4 ++++ target/riscv/trace-events | 6 ++++++ target/riscv/translate.c | 2 ++ 4 files changed, 13 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ee868c5fcb..66b26cbe8b 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -65,6 +65,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); generate_exception(ctx, RISCV_EXCP_SW_CHECK); + trace_zicfilp_unaligned_lpad_instr((uint64_t) ctx->base.pc_next); return true; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 54baa3a966..6a54c6c24d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -283,6 +284,8 @@ void helper_cfi_check_landing_pad(CPURISCVState *env, int lbl) * greater than 31 and then shift 12 right */ if (lbl && (lbl != ((env->gpr[xT2] & 0xFFFFFFFF) >> 12))) { + trace_zicfilp_lpad_reg_mismatch(lbl, + (env->gpr[xT2] & 0xFFFFFFFF) >> 12); env->sw_check_code = RISCV_EXCP_SW_CHECK_FCFI_TVAL; riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } @@ -295,6 +298,7 @@ void helper_sschk_mismatch(CPURISCVState *env, target_ulong rs1, target_ulong ssra) { if (rs1 != ssra) { + trace_zicfiss_sspopchk_reg_mismatch((uint64_t)ssra, (uint64_t) rs1); env->sw_check_code = RISCV_EXCP_SW_CHECK_BCFI_TVAL; riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..842349ecb9 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,9 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64 + +# zicfiss/lp +zicfiss_sspopchk_reg_mismatch(uint64_t ssra, uint64_t rs1) "shadow_stack_ra: 0x%" PRIx64 ", rs1: 0x%" PRIx64 +zicfilp_missing_lpad_instr(uint64_t pc_first) "pc_first: 0x%" PRIx64 +zicfilp_unaligned_lpad_instr(uint64_t pc_next) "pc_next: 0x%" PRIx64 +zicfilp_lpad_reg_mismatch(int lpad_label, int t2_label) "lpad_label: 0x%x, t2_label: 0x%x" diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ad0f841807..958a1578d4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "semihosting/semihost.h" #include "internals.h" +#include "trace.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -1380,6 +1381,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * illegal instruction exception. */ tcg_set_insn_param(cfi_lp_check, 1, tcgv_i32_arg(tcg_constant_i32(1))); + trace_zicfilp_missing_lpad_instr((uint64_t) ctx->base.pc_first); } } -- 2.44.0