From: Warner Losh <i...@bsdimp.com>
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <i...@bsdimp.com>
Signed-off-by: Ajeet Singh <itac...@freebsd.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20240916155119.14610-13-itac...@freebsd.org>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
---
bsd-user/riscv/target.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 bsd-user/riscv/target.h
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h
new file mode 100644
index 0000000000..036ddd185e
--- /dev/null
+++ b/bsd-user/riscv/target.h
@@ -0,0 +1,20 @@
+/*
+ * Riscv64 general target stuff that's common to all aarch details
+ *
+ * Copyright (c) 2022 M. Warner Losh <i...@bsdimp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_H
+#define TARGET_H
+
+/*
+ * riscv64 ABI does not 'lump' the registers for 64-bit args.
+ */
+static inline bool regpairs_aligned(void *cpu_env)
+{
+ return false;
+}
+
+#endif /* TARGET_H */
--
2.46.2
