From: Alistair Francis <alistai...@gmail.com> The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748 Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> Message-ID: <20240823003231.3522113-1-alistair.fran...@wdc.com> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f8189bcf0..a1ca12077f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -680,6 +680,11 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.ext_zicsr = true; cpu->cfg.pmp = true; cpu->cfg.ext_smepmp = true; + + cpu->cfg.ext_zba = true; + cpu->cfg.ext_zbb = true; + cpu->cfg.ext_zbc = true; + cpu->cfg.ext_zbs = true; } static void rv32_imafcu_nommu_cpu_init(Object *obj) -- 2.46.2
