On Fri, 1 Nov 2024 at 20:46, Daniel Henrique Barboza <[email protected]> wrote: > Pierrick, I copied the description of this function from the riscv-isa spec > and put in a comment. This is how it would look like: > > $ git diff > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index feb650549a..969eb56c53 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -183,8 +183,25 @@ static void riscv_iommu_pri(RISCVIOMMUState *s, > } > } > > -/* Portable implementation of pext_u64, bit-mask extraction. */ > -static uint64_t _pext_u64(uint64_t val, uint64_t ext) > +/* > + * Discards all bits from 'val' whose matching bits in the same > + * positions in the mask 'ext' are zeros, and packs the remaining > + * bits from 'val' contiguously at the least-significant end of the > + * result, keeping the same bit order as 'val' and filling any > + * other bits at the most-significant end of the result with zeros. > + * > + * For example, for the following 'val' and 'ext', the return 'ret' > + * will be: > + * > + * val = a b c d e f g h > + * ext = 1 0 1 0 0 1 1 0 > + * ret = 0 0 0 0 a c f g > + * > + * This function, taken from the riscv-iommu 1.0 spec, section 2.3.3 > + * "Process to translate addresses of MSIs", is similar to bit manip > + * function PEXT (Parallel bits extract) from x86. > + */ > +static uint64_t riscv_iommu_pext_u64(uint64_t val, uint64_t ext)
That looks great, thanks. -- PMM
