On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The memory map for AST2700 A1 remains compatible with AST2700 A0.
> However, the IRQ mapping has been updated for AST2700 A1, with GIC
> interrupts
> now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
>
> Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the
> AST2700 EVB
> machine. Add "aspeed_soc_ast2700_class_init" to initialize the
> AST2700 A1 SoC.
>
> Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
> ---
> hw/arm/aspeed.c | 24 +++++++++++++
> hw/arm/aspeed_ast27x0.c | 80
> +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 104 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 402d55c556..254fa5316d 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1672,6 +1672,26 @@ static void
> aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
> mc->default_ram_size = 1 * GiB;
> aspeed_machine_class_init_cpus_defaults(mc);
> }
> +
> +static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc,
> void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> + mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
> + amc->soc_name = "ast2700-a1";
> + amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> + amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> + amc->fmc_model = "w25q01jvq";
> + amc->spi_model = "w25q512jv";
> + amc->num_cs = 2;
> + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON |
> ASPEED_MAC2_ON;
> + amc->uart_default = ASPEED_DEV_UART12;
> + amc->i2c_init = ast2700_evb_i2c_init;
> + mc->default_ram_size = 1 * GiB;
> + aspeed_machine_class_init_cpus_defaults(mc);
> +}
> +
> #endif
>
> static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass
> *oc,
> @@ -1798,6 +1818,10 @@ static const TypeInfo aspeed_machine_types[] =
> {
> .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
> .parent = TYPE_ASPEED_MACHINE,
> .class_init = aspeed_machine_ast2700a0_evb_class_init,
> + }, {
> + .name = MACHINE_TYPE_NAME("ast2700-evb"),
> + .parent = TYPE_ASPEED_MACHINE,
> + .class_init = aspeed_machine_ast2700_evb_class_init,
> #endif
> }, {
> .name = TYPE_ASPEED_MACHINE,
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index b32c4fcc35..e0a29c9053 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -119,6 +119,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =
> {
> [ASPEED_DEV_SDHCI] = 133,
> };
>
> +static const int aspeed_soc_ast2700_irqmap[] = {
> + [ASPEED_DEV_UART0] = 196,
> + [ASPEED_DEV_UART1] = 196,
> + [ASPEED_DEV_UART2] = 196,
> + [ASPEED_DEV_UART3] = 196,
> + [ASPEED_DEV_UART4] = 8,
> + [ASPEED_DEV_UART5] = 196,
> + [ASPEED_DEV_UART6] = 196,
> + [ASPEED_DEV_UART7] = 196,
> + [ASPEED_DEV_UART8] = 196,
> + [ASPEED_DEV_UART9] = 196,
> + [ASPEED_DEV_UART10] = 196,
> + [ASPEED_DEV_UART11] = 196,
> + [ASPEED_DEV_UART12] = 196,
> + [ASPEED_DEV_FMC] = 195,
> + [ASPEED_DEV_SDMC] = 0,
> + [ASPEED_DEV_SCU] = 12,
> + [ASPEED_DEV_ADC] = 194,
> + [ASPEED_DEV_XDMA] = 5,
> + [ASPEED_DEV_EMMC] = 15,
> + [ASPEED_DEV_GPIO] = 194,
> + [ASPEED_DEV_RTC] = 13,
> + [ASPEED_DEV_TIMER1] = 16,
> + [ASPEED_DEV_TIMER2] = 17,
> + [ASPEED_DEV_TIMER3] = 18,
> + [ASPEED_DEV_TIMER4] = 19,
> + [ASPEED_DEV_TIMER5] = 20,
> + [ASPEED_DEV_TIMER6] = 21,
> + [ASPEED_DEV_TIMER7] = 22,
> + [ASPEED_DEV_TIMER8] = 23,
> + [ASPEED_DEV_WDT] = 195,
> + [ASPEED_DEV_PWM] = 195,
> + [ASPEED_DEV_LPC] = 192,
> + [ASPEED_DEV_IBT] = 192,
> + [ASPEED_DEV_I2C] = 194,
> + [ASPEED_DEV_PECI] = 197,
> + [ASPEED_DEV_ETH1] = 196,
> + [ASPEED_DEV_ETH2] = 196,
> + [ASPEED_DEV_ETH3] = 196,
> + [ASPEED_DEV_HACE] = 4,
> + [ASPEED_DEV_KCS] = 192,
> + [ASPEED_DEV_DP] = 28,
> + [ASPEED_DEV_I3C] = 195,
> + [ASPEED_DEV_SDHCI] = 197,
> +};
Bit of a nit, but can we sort this table? Perhaps by interrupt value?
Andrew
