Hi Shameer,
On 3/12/25 6:28 PM, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Daniel P. Berrangé <[email protected]> >> Sent: Wednesday, March 12, 2025 4:39 PM >> To: Shameerali Kolothum Thodi <[email protected]> >> Cc: [email protected]; [email protected]; qemu- >> [email protected]; [email protected]; [email protected]; >> [email protected]; [email protected]; [email protected]; >> [email protected]; [email protected]; Linuxarm >> <[email protected]>; Wangzhou (B) <[email protected]>; >> jiangkunkun <[email protected]>; Jonathan Cameron >> <[email protected]>; [email protected] >> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb- >> pcie bus >> >> On Wed, Mar 12, 2025 at 04:34:18PM +0000, Shameerali Kolothum Thodi >> wrote: >>> Hi Eric, >>> >>>> -----Original Message----- >>>> From: Eric Auger <[email protected]> >>>> Sent: Wednesday, March 12, 2025 4:08 PM >>>> To: Shameerali Kolothum Thodi >>>> <[email protected]>; [email protected]; >>>> [email protected] >>>> Cc: [email protected]; [email protected]; [email protected]; >>>> [email protected]; [email protected]; [email protected]; >>>> [email protected]; [email protected]; Linuxarm >>>> <[email protected]>; Wangzhou (B) <[email protected]>; >>>> jiangkunkun <[email protected]>; Jonathan Cameron >>>> <[email protected]>; [email protected] >>>> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a >> pxb- >>>> pcie bus >>>> >>>> Hi Shameer, >>>> >>>> >>>> On 3/11/25 3:10 PM, Shameer Kolothum wrote: >>>>> User must associate a pxb-pcie root bus to smmuv3-accel >>>>> and that is set as the primary-bus for the smmu dev. >>>> why do we require a pxb-pcie root bus? why can't pci.0 root bus be used >>>> for simpler use cases (ie. I just want to passthough a NIC in >>>> accelerated mode). Or may pci.0 is also called a pax-pcie root bus? >>> The idea was since pcie.0 is the default RC with virt, leave that to cases >> where >>> we want to attach any emulated devices and use pxb-pcie based RCs for >> vfio-pci. >> >> The majority of management applications will never do anything other >> than a flat PCI(e) topology by default. Some might enable pxb-pcie as >> an optional but plenty won't ever support it. If you want to maximise >> the potential usefulness of the ssmmuv3-accel, and it is technically >> viable, it would be worth permitting choice of attachment to the root >> bus as an alteranative to the pxb. > Ok. I will look into this. Though I am not sure when we have smmuv3-accel > to pcie.0 we can still have additional smmuv3-accel with pxb-pcie or not. > It looks like pxb-pcie will be plugged into pcie.0. And if that is the case > IORT mappings will be difficult I guess. I need to double check. Indeed it makes things more difficult in terms of id mapping but I think it would bring some benefits to be able to plug the accel smmu on pci.0 too. some logic should be there already because you can bypass the SMMU on a given pxb while enabled on pci.0: see [PATCH v5 0/9] IOMMU: Add support for IOMMU Bypass Feature <https://lore.kernel.org/all/[email protected]/#r> https://lore.kernel.org/all/[email protected]/ Eric > > Thanks, > Shameer
