Hi Eric, > -----Original Message----- > From: Eric Auger <[email protected]> > Sent: Wednesday, March 12, 2025 4:42 PM > To: Shameerali Kolothum Thodi > <[email protected]>; [email protected]; > [email protected] > Cc: [email protected]; [email protected]; [email protected]; > [email protected]; [email protected]; [email protected]; > [email protected]; [email protected]; Linuxarm > <[email protected]>; Wangzhou (B) <[email protected]>; > jiangkunkun <[email protected]>; Jonathan Cameron > <[email protected]>; [email protected] > Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb- > pcie bus > > > > > On 3/12/25 5:34 PM, Shameerali Kolothum Thodi wrote: > > Hi Eric, > > > >> -----Original Message----- > >> From: Eric Auger <[email protected]> > >> Sent: Wednesday, March 12, 2025 4:08 PM > >> To: Shameerali Kolothum Thodi > >> <[email protected]>; [email protected]; > >> [email protected] > >> Cc: [email protected]; [email protected]; [email protected]; > >> [email protected]; [email protected]; [email protected]; > >> [email protected]; [email protected]; Linuxarm > >> <[email protected]>; Wangzhou (B) <[email protected]>; > >> jiangkunkun <[email protected]>; Jonathan Cameron > >> <[email protected]>; [email protected] > >> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a > pxb- > >> pcie bus > >> > >> Hi Shameer, > >> > >> > >> On 3/11/25 3:10 PM, Shameer Kolothum wrote: > >>> User must associate a pxb-pcie root bus to smmuv3-accel > >>> and that is set as the primary-bus for the smmu dev. > >> why do we require a pxb-pcie root bus? why can't pci.0 root bus be used > >> for simpler use cases (ie. I just want to passthough a NIC in > >> accelerated mode). Or may pci.0 is also called a pax-pcie root bus? > > The idea was since pcie.0 is the default RC with virt, leave that to cases > where > > we want to attach any emulated devices and use pxb-pcie based RCs for > vfio-pci. > yes but for simpler use case you may not want the extra pain to > instantiate a pxb-pcie device. Actually libvirt does not instantiate it > by default. > > > >> Besides, why do we put the constraint to plug on a root bus. I know that > >> at this point we always plug to pci.0 but with the new -device option it > >> would be possible to plug it anywhere in the pcie hierarchy. At SOC > >> level can't an SMMU be plugged anywhere protecting just a few RIDs? > > In my understanding normally(or atleast in the most common cases) it is > attached > > to root complexes. Also IORT mappings are at the root complex level, > right? > Yes I do agree the IORT describes ID mappings between RC and SMMU but > the actual ID mappings allow you to be much more precise and state that > a given SMMU only translates few RIDs within that RID space. If you > force the device bus to be a root bus you can't model that anymore. >
Do we really need to support that? What if the user then have another smmuv3-accel in the associated upstream buses/RC as well? Not sure how to handle that. Thanks, Shameer
