This patch series contains several sstc fixes:
(1) Writing to ACLINT mtime should also update the period of S/VS-mode
timer, just like M-mode timer.
(2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
(3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
which should update the timer and IRQ pending bits.
Jim Shu (4):
target/riscv: Add the checking into stimecmp write function.
hw/intc: riscv_aclint: Fix mtime write for sstc extension
target/riscv: Fix VSTIP bit in sstc extension.
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
hw/intc/riscv_aclint.c | 5 +++
target/riscv/csr.c | 53 ++++++++++++++++++++++++++++-
target/riscv/time_helper.c | 70 ++++++++++++++++++++++++++++++++++++--
target/riscv/time_helper.h | 1 +
4 files changed, 126 insertions(+), 3 deletions(-)
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2.17.1
