On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard <ant...@tenstorrent.com>
>
> Handle the overlap of source registers with different EEWs.
>
> Signed-off-by: Anton Blanchard <ant...@tenstorrent.com>
> Reviewed-by: Max Chou <max.c...@sifive.com>
> Signed-off-by: Max Chou <max.c...@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2b6077ac067..ec34d0d8c47 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -436,9 +436,10 @@ static bool vext_check_sss(DisasContext *s, int vd, int
> vs1, int vs2, int vm)
> require_align(vs1, s->lmul);
> }
>
> -static bool vext_check_ms(DisasContext *s, int vd, int vs)
> +static bool vext_check_ms(DisasContext *s, int vd, int vs, int vm)
> {
> - bool ret = require_align(vs, s->lmul);
> + bool ret = require_align(vs, s->lmul) &&
> + vext_check_input_eew(s, vs, s->sew, -1, 0, vm);
> if (vd != vs) {
> ret &= require_noover(vd, 0, vs, s->lmul);
> }
> @@ -461,9 +462,10 @@ static bool vext_check_ms(DisasContext *s, int vd, int
> vs)
> * with a mask value (e.g., comparisons) or the scalar result
> * of a reduction. (Section 5.3)
> */
> -static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
> +static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2, int vm)
> {
> - bool ret = vext_check_ms(s, vd, vs2) &&
> + bool ret = vext_check_ms(s, vd, vs2, vm) &&
> + vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
> require_align(vs1, s->lmul);
> if (vd != vs1) {
> ret &= require_noover(vd, 0, vs1, s->lmul);
> @@ -2040,7 +2042,7 @@ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr
> *a)
> {
> return require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_mss(s, a->rd, a->rs1, a->rs2);
> + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
> }
>
> GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
> @@ -2076,7 +2078,7 @@ static bool opivx_vmadc_check(DisasContext *s, arg_rmrr
> *a)
> {
> return require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_ms(s, a->rd, a->rs2);
> + vext_check_ms(s, a->rd, a->rs2, a->vm);
> }
>
> GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
> @@ -2250,7 +2252,7 @@ static bool opivv_cmp_check(DisasContext *s, arg_rmrr
> *a)
> {
> return require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_mss(s, a->rd, a->rs1, a->rs2);
> + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
> }
>
> GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
> @@ -2264,7 +2266,7 @@ static bool opivx_cmp_check(DisasContext *s, arg_rmrr
> *a)
> {
> return require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_ms(s, a->rd, a->rs2);
> + vext_check_ms(s, a->rd, a->rs2, a->vm);
> }
>
> GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
> @@ -2972,7 +2974,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr
> *a)
> return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_mss(s, a->rd, a->rs1, a->rs2);
> + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
> }
>
> GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
> @@ -2985,7 +2987,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr
> *a)
> return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_ms(s, a->rd, a->rs2);
> + vext_check_ms(s, a->rd, a->rs2, a->vm);
> }
>
> GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
Reviewed-by: Nutty Liu<liujin...@lanxincomputing.com>
Thanks,
Nutty
