On Tue, Jul 8, 2025 at 11:37 AM Xu Lu <luxu.ker...@bytedance.com> wrote:
>
> When supervisor CSRs are accessed from VU-mode, a virtual instruction
> exception should be raised instead of an illegal instruction.
>
> Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
> Signed-off-by: Xu Lu <luxu.ker...@bytedance.com>
LGTM.
Reviewed-by: Anup Patel <apa...@ventanamicro.com>
Regards,
Anup
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8631be97c5..9bebfae3f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5577,7 +5577,7 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
>
> csr_priv = get_field(csrno, 0x300);
> if (!env->debugger && (effective_priv < csr_priv)) {
> - if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
> + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> --
> 2.20.1
>
