On Wed, Oct 1, 2025 at 5:45 PM Anton Johansson via <[email protected]> wrote: > > This commits groups together all CPUArchState fields whose behaviour can > be retained by simply changing the size of the field. > > Note, senvcfg is defined to be SXLEN bits wide, but is widened to 64 > bits to match henvcfg and menvcfg. Next, [m|h]edeleg are changed to > 64 bits as defined privileged specification, and hvictl is fixed to 32 > bits which holds all relevant values, see HVICTL_VALID_MASK. The > remaining fields touched in the commit are widened from [H|S|M]XLEN > to 64-bit. > > Note, the cpu/hyper, cpu/envcfg, cpu/jvt, and cpu VMSTATE versions are > bumped, breaking migration from older versions. > > References to the privileged/unprivileged RISCV specification refer to > version 20250508. > > Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 78 +++++++++++++++++++-------------------- > target/riscv/machine.c | 84 +++++++++++++++++++++--------------------- > 2 files changed, 81 insertions(+), 81 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f05e06bb70..736e4f6daa 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -254,7 +254,7 @@ struct CPUArchState { > /* 128-bit helpers upper part return value */ > target_ulong retxh; > > - target_ulong jvt; > + uint64_t jvt; > > /* elp state for zicfilp extension */ > bool elp; > @@ -271,7 +271,7 @@ struct CPUArchState { > target_ulong priv; > /* CSRs for execution environment configuration */ > uint64_t menvcfg; > - target_ulong senvcfg; > + uint64_t senvcfg; > > #ifndef CONFIG_USER_ONLY > /* This contains QEMU specific information about the virt state. */ > @@ -313,18 +313,18 @@ struct CPUArchState { > */ > uint64_t vsie; > > - target_ulong satp; /* since: priv-1.10.0 */ > - target_ulong stval; > - target_ulong medeleg; > + uint64_t satp; /* since: priv-1.10.0 */ > + uint64_t stval; > + uint64_t medeleg; > > - target_ulong stvec; > - target_ulong sepc; > - target_ulong scause; > + uint64_t stvec; > + uint64_t sepc; > + uint64_t scause; > > - target_ulong mtvec; > - target_ulong mepc; > - target_ulong mcause; > - target_ulong mtval; /* since: priv-1.10.0 */ > + uint64_t mtvec; > + uint64_t mepc; > + uint64_t mcause; > + uint64_t mtval; /* since: priv-1.10.0 */ > > uint64_t mctrctl; > uint32_t sctrdepth; > @@ -346,13 +346,13 @@ struct CPUArchState { > uint64_t mvip; > > /* Hypervisor CSRs */ > - target_ulong hstatus; > - target_ulong hedeleg; > + uint64_t hstatus; > + uint64_t hedeleg; > uint64_t hideleg; > uint32_t hcounteren; > - target_ulong htval; > - target_ulong htinst; > - target_ulong hgatp; > + uint64_t htval; > + uint64_t htinst; > + uint64_t hgatp; > target_ulong hgeie; > target_ulong hgeip; > uint64_t htimedelta; > @@ -366,7 +366,7 @@ struct CPUArchState { > uint64_t hvip; > > /* Hypervisor controlled virtual interrupt priorities */ > - target_ulong hvictl; > + uint32_t hvictl; > uint8_t hviprio[64]; > > /* Upper 64-bits of 128-bit CSRs */ > @@ -379,26 +379,26 @@ struct CPUArchState { > * For RV64 this is a 64-bit vsstatus. > */ > uint64_t vsstatus; > - target_ulong vstvec; > - target_ulong vsscratch; > - target_ulong vsepc; > - target_ulong vscause; > - target_ulong vstval; > - target_ulong vsatp; > + uint64_t vstvec; > + uint64_t vsscratch; > + uint64_t vsepc; > + uint64_t vscause; > + uint64_t vstval; > + uint64_t vsatp; > > /* AIA VS-mode CSRs */ > target_ulong vsiselect; > > - target_ulong mtval2; > - target_ulong mtinst; > + uint64_t mtval2; > + uint64_t mtinst; > > /* HS Backup CSRs */ > - target_ulong stvec_hs; > - target_ulong sscratch_hs; > - target_ulong sepc_hs; > - target_ulong scause_hs; > - target_ulong stval_hs; > - target_ulong satp_hs; > + uint64_t stvec_hs; > + uint64_t sscratch_hs; > + uint64_t sepc_hs; > + uint64_t scause_hs; > + uint64_t stval_hs; > + uint64_t satp_hs; > uint64_t mstatus_hs; > > /* > @@ -435,8 +435,8 @@ struct CPUArchState { > > PMUFixedCtrState pmu_fixed_ctrs[2]; > > - target_ulong sscratch; > - target_ulong mscratch; > + uint64_t sscratch; > + uint64_t mscratch; > > /* Sstc CSRs */ > uint64_t stimecmp; > @@ -506,11 +506,11 @@ struct CPUArchState { > #endif /* CONFIG_KVM */ > > /* RNMI */ > - target_ulong mnscratch; > - target_ulong mnepc; > - target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ > - target_ulong mnstatus; > - target_ulong rnmip; > + uint64_t mnscratch; > + uint64_t mnepc; > + uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */ > + uint64_t mnstatus; > + uint64_t rnmip; > uint64_t rnmi_irqvec; > uint64_t rnmi_excpvec; > }; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 1600ec44f0..99e46c3136 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -80,17 +80,17 @@ static bool hyper_needed(void *opaque) > > static const VMStateDescription vmstate_hyper = { > .name = "cpu/hyper", > - .version_id = 4, > - .minimum_version_id = 4, > + .version_id = 5, > + .minimum_version_id = 5, > .needed = hyper_needed, > .fields = (const VMStateField[]) { > - VMSTATE_UINTTL(env.hstatus, RISCVCPU), > - VMSTATE_UINTTL(env.hedeleg, RISCVCPU), > + VMSTATE_UINT64(env.hstatus, RISCVCPU), > + VMSTATE_UINT64(env.hedeleg, RISCVCPU), > VMSTATE_UINT64(env.hideleg, RISCVCPU), > VMSTATE_UINT32(env.hcounteren, RISCVCPU), > - VMSTATE_UINTTL(env.htval, RISCVCPU), > - VMSTATE_UINTTL(env.htinst, RISCVCPU), > - VMSTATE_UINTTL(env.hgatp, RISCVCPU), > + VMSTATE_UINT64(env.htval, RISCVCPU), > + VMSTATE_UINT64(env.htinst, RISCVCPU), > + VMSTATE_UINT64(env.hgatp, RISCVCPU), > VMSTATE_UINTTL(env.hgeie, RISCVCPU), > VMSTATE_UINTTL(env.hgeip, RISCVCPU), > VMSTATE_UINT64(env.hvien, RISCVCPU), > @@ -98,28 +98,28 @@ static const VMStateDescription vmstate_hyper = { > VMSTATE_UINT64(env.htimedelta, RISCVCPU), > VMSTATE_UINT64(env.vstimecmp, RISCVCPU), > > - VMSTATE_UINTTL(env.hvictl, RISCVCPU), > + VMSTATE_UINT32(env.hvictl, RISCVCPU), > VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), > > VMSTATE_UINT64(env.vsstatus, RISCVCPU), > - VMSTATE_UINTTL(env.vstvec, RISCVCPU), > - VMSTATE_UINTTL(env.vsscratch, RISCVCPU), > - VMSTATE_UINTTL(env.vsepc, RISCVCPU), > - VMSTATE_UINTTL(env.vscause, RISCVCPU), > - VMSTATE_UINTTL(env.vstval, RISCVCPU), > - VMSTATE_UINTTL(env.vsatp, RISCVCPU), > + VMSTATE_UINT64(env.vstvec, RISCVCPU), > + VMSTATE_UINT64(env.vsscratch, RISCVCPU), > + VMSTATE_UINT64(env.vsepc, RISCVCPU), > + VMSTATE_UINT64(env.vscause, RISCVCPU), > + VMSTATE_UINT64(env.vstval, RISCVCPU), > + VMSTATE_UINT64(env.vsatp, RISCVCPU), > VMSTATE_UINTTL(env.vsiselect, RISCVCPU), > VMSTATE_UINT64(env.vsie, RISCVCPU), > > - VMSTATE_UINTTL(env.mtval2, RISCVCPU), > - VMSTATE_UINTTL(env.mtinst, RISCVCPU), > + VMSTATE_UINT64(env.mtval2, RISCVCPU), > + VMSTATE_UINT64(env.mtinst, RISCVCPU), > > - VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), > - VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), > - VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), > - VMSTATE_UINTTL(env.scause_hs, RISCVCPU), > - VMSTATE_UINTTL(env.stval_hs, RISCVCPU), > - VMSTATE_UINTTL(env.satp_hs, RISCVCPU), > + VMSTATE_UINT64(env.stvec_hs, RISCVCPU), > + VMSTATE_UINT64(env.sscratch_hs, RISCVCPU), > + VMSTATE_UINT64(env.sepc_hs, RISCVCPU), > + VMSTATE_UINT64(env.scause_hs, RISCVCPU), > + VMSTATE_UINT64(env.stval_hs, RISCVCPU), > + VMSTATE_UINT64(env.satp_hs, RISCVCPU), > VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), > > VMSTATE_END_OF_LIST() > @@ -290,12 +290,12 @@ static bool envcfg_needed(void *opaque) > > static const VMStateDescription vmstate_envcfg = { > .name = "cpu/envcfg", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .needed = envcfg_needed, > .fields = (const VMStateField[]) { > VMSTATE_UINT64(env.menvcfg, RISCVCPU), > - VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > + VMSTATE_UINT64(env.senvcfg, RISCVCPU), > VMSTATE_UINT64(env.henvcfg, RISCVCPU), > VMSTATE_END_OF_LIST() > } > @@ -355,11 +355,11 @@ static bool jvt_needed(void *opaque) > > static const VMStateDescription vmstate_jvt = { > .name = "cpu/jvt", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .needed = jvt_needed, > .fields = (const VMStateField[]) { > - VMSTATE_UINTTL(env.jvt, RISCVCPU), > + VMSTATE_UINT64(env.jvt, RISCVCPU), > VMSTATE_END_OF_LIST() > } > }; > @@ -402,8 +402,8 @@ static const VMStateDescription vmstate_ssp = { > > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > - .version_id = 10, > - .minimum_version_id = 10, > + .version_id = 11, > + .minimum_version_id = 11, > .post_load = riscv_cpu_post_load, > .fields = (const VMStateField[]) { > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > @@ -434,16 +434,16 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINT64(env.mvip, RISCVCPU), > VMSTATE_UINT64(env.sie, RISCVCPU), > VMSTATE_UINT64(env.mideleg, RISCVCPU), > - VMSTATE_UINTTL(env.satp, RISCVCPU), > - VMSTATE_UINTTL(env.stval, RISCVCPU), > - VMSTATE_UINTTL(env.medeleg, RISCVCPU), > - VMSTATE_UINTTL(env.stvec, RISCVCPU), > - VMSTATE_UINTTL(env.sepc, RISCVCPU), > - VMSTATE_UINTTL(env.scause, RISCVCPU), > - VMSTATE_UINTTL(env.mtvec, RISCVCPU), > - VMSTATE_UINTTL(env.mepc, RISCVCPU), > - VMSTATE_UINTTL(env.mcause, RISCVCPU), > - VMSTATE_UINTTL(env.mtval, RISCVCPU), > + VMSTATE_UINT64(env.satp, RISCVCPU), > + VMSTATE_UINT64(env.stval, RISCVCPU), > + VMSTATE_UINT64(env.medeleg, RISCVCPU), > + VMSTATE_UINT64(env.stvec, RISCVCPU), > + VMSTATE_UINT64(env.sepc, RISCVCPU), > + VMSTATE_UINT64(env.scause, RISCVCPU), > + VMSTATE_UINT64(env.mtvec, RISCVCPU), > + VMSTATE_UINT64(env.mepc, RISCVCPU), > + VMSTATE_UINT64(env.mcause, RISCVCPU), > + VMSTATE_UINT64(env.mtval, RISCVCPU), > VMSTATE_UINTTL(env.miselect, RISCVCPU), > VMSTATE_UINTTL(env.siselect, RISCVCPU), > VMSTATE_UINT32(env.scounteren, RISCVCPU), > @@ -454,8 +454,8 @@ const VMStateDescription vmstate_riscv_cpu = { > vmstate_pmu_ctr_state, PMUCTRState), > VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), > VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, > RV_MAX_MHPMEVENTS), > - VMSTATE_UINTTL(env.sscratch, RISCVCPU), > - VMSTATE_UINTTL(env.mscratch, RISCVCPU), > + VMSTATE_UINT64(env.sscratch, RISCVCPU), > + VMSTATE_UINT64(env.mscratch, RISCVCPU), > VMSTATE_UINT64(env.stimecmp, RISCVCPU), > > VMSTATE_END_OF_LIST() > -- > 2.51.0 > >
