Hi Eric, > -----Original Message----- > From: Eric Auger <[email protected]> > Sent: 03 November 2025 15:07 > To: Shameer Kolothum <[email protected]>; qemu- > [email protected]; [email protected] > Cc: [email protected]; Jason Gunthorpe <[email protected]>; Nicolin > Chen <[email protected]>; [email protected]; [email protected]; > Nathan Chen <[email protected]>; Matt Ochs <[email protected]>; > [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; [email protected]; [email protected]; > Krishnakant Jaju <[email protected]> > Subject: Re: [PATCH v5 26/32] hw/arm/smmuv3-accel: Add a property to > specify RIL support > > External email: Use caution opening links or attachments > > > Hi Shameer, > > On 10/31/25 11:49 AM, Shameer Kolothum wrote: > > Currently QEMU SMMUv3 has RIL support by default. But if accelerated > > mode is enabled, RIL has to be compatible with host SMMUv3 support. > > > > Add a property so that the user can specify this. > > > > Reviewed-by: Jonathan Cameron <[email protected]> > > Tested-by: Zhangfei Gao <[email protected]> > > Signed-off-by: Shameer Kolothum <[email protected]> > > I have not seen any reply on > https://lore.kernel.org/all/b6105534-4a17-4700-bb0b- > [email protected]/
Sorry, looks like I missed to reply. > I guess you chose to restrict RIL to accel only. Yes. I have updated the description. About AIDR consistency check, > did you have a look? I have added that check in patch #19. But Zhangfei has reported a problem with that as his hardware reports AIDR = 0. . Please take a look that discussion. Thanks, Shameer
