Hi, > This patch was dropped in the v2 pull request, @Djordje can you fix > this in the next patch submission
Yes, sure. Thanks for the comments! Djordje ________________________________________ From: Alistair Francis <[email protected]> Sent: Thursday, November 6, 2025 11:57 PM To: Philippe Mathieu-Daudé <[email protected]> Cc: [email protected] <[email protected]>; Anton Johansson <[email protected]>; Djordje Todorovic <[email protected]>; Chao-ying Fu <[email protected]>; Daniel Henrique Barboza <[email protected]>; Alistair Francis <[email protected]> Subject: Re: [PULL 26/37] hw/misc: Add RISC-V CMGCR device implementation CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe. On Wed, Nov 5, 2025 at 8:15 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > On 23/10/25 06:35, [email protected] wrote: > > From: Djordje Todorovic <[email protected]> > > > > Add RISC-V implementation of the Coherent Manager Global Control > > Register (CMGCR) device. It is based on the existing MIPS CMGCR > > implementation but adapted for RISC-V systems. > > > > The CMGCR device provides global system control for multi-core > > configurations in RISC-V systems. > > > > This is needed for the MIPS BOSTON AIA board. > > > > Signed-off-by: Chao-ying Fu <[email protected]> > > Signed-off-by: Djordje Todorovic <[email protected]> > > Reviewed-by: Daniel Henrique Barboza <[email protected]> > > Message-ID: <[email protected]> > > Signed-off-by: Alistair Francis <[email protected]> > > --- > > include/hw/misc/riscv_cmgcr.h | 50 +++++++ > > hw/misc/riscv_cmgcr.c | 248 ++++++++++++++++++++++++++++++++++ > > hw/misc/Kconfig | 9 ++ > > hw/misc/meson.build | 2 + > > 4 files changed, 309 insertions(+) > > create mode 100644 include/hw/misc/riscv_cmgcr.h > > create mode 100644 hw/misc/riscv_cmgcr.c > > > > +static inline void update_gcr_base(RISCVGCRState *gcr, uint64_t val) > > +{ > > + gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; > > + memory_region_set_address(&gcr->iomem, gcr->gcr_base); > > + > > + /* > > + * For boston-aia, cpc_base is set to gcr_base + 0x8001 to enable > > + * cpc automatically. > > + */ > > + update_cpc_base(gcr, val + 0x8001); > > +} > > + > > +/* Read GCR registers */ > > +static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) > > +{ > > + RISCVGCRState *gcr = (RISCVGCRState *) opaque; > > + > > + switch (addr) { > > + /* Global Control Block Register */ > > + case GCR_CONFIG_OFS: > > + /* Set PCORES to 0 */ > > + return 0; > > + case GCR_BASE_OFS: > > + return gcr->gcr_base; > > + case GCR_REV_OFS: > > + return gcr->gcr_rev; > > + case GCR_CPC_STATUS_OFS: > > + return is_cpc_connected(gcr); > > + case GCR_L2_CONFIG_OFS: > > + /* L2 BYPASS */ > > + return GCR_L2_CONFIG_BYPASS_MSK; > > + default: > > + qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" > > HWADDR_PRIx > > + "\n", size, addr); > > + } > > + return 0; > > +} > > + > > +static inline target_ulong get_exception_base(RISCVGCRVPState *vps) > > +{ > > + return vps->reset_base & GCR_CL_RESET_BASE_RESETBASE_MSK; > > +} > > + > > +/* Write GCR registers */ > > +static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned > > size) > > +{ > > + RISCVGCRState *gcr = (RISCVGCRState *)opaque; > > + RISCVGCRVPState *current_vps; > > + int cpu_index, c, h; > > + > > + for (c = 0; c < gcr->num_core; c++) { > > + for (h = 0; h < gcr->num_hart; h++) { > > + if (addr == RISCV_CLCB_OFS + c * RISCV_CORE_REG_STRIDE + h * > > 8) { > > + cpu_index = c * gcr->num_hart + h; > > + current_vps = &gcr->vps[cpu_index]; > > + current_vps->reset_base = data & GCR_CL_RESET_BASE_MSK; > > + cpu_set_exception_base(cpu_index + gcr->cluster_id * > > + gcr->num_core * gcr->num_hart, > > + get_exception_base(current_vps)); > > + return; > > + } > > + } > > + } > > + > > + switch (addr) { > > + case GCR_BASE_OFS: > > + update_gcr_base(gcr, data); > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" > > HWADDR_PRIx > > + " 0x%" PRIx64 "\n", size, addr, data); > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps gcr_ops = { > > + .read = gcr_read, > > + .write = gcr_write, > > + .endianness = DEVICE_NATIVE_ENDIAN, > > Dubious DEVICE_NATIVE_ENDIAN use, do you mean DEVICE_LITTLE_ENDIAN? > > Maybe we can alter checkpatch to no accept new DEVICE_NATIVE_ENDIAN > in our code base. Ah good catch, this could be the s390 issue. This patch was dropped in the v2 pull request, @Djordje can you fix this in the next patch submission Alistair
