Yodel Eldar <[email protected]> writes: (add Florians to CC)
> On 11/11/2025 04:54, Alex Bennée wrote: >> The datasheet doesn't explicitly say that TXFR_LEN has to be word >> aligned but the fact there is a DMA_D_WIDTH flag to select between 32 >> bit and 128 bit strongly implies that is how it works. The downstream > > At the bottom of page 38, the datasheet [1] states "the DMA can deal > with byte aligned transfers and will minimise bus traffic by buffering > and packing misaligned accesses." > > IIUC, the *_WIDTH info fields are implied as maxima. > > [1] https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf That reads ambiguously - you could start a misaligned n*WIDTH transfer and the hardware will write bytes until aligned? If it does indeed work with byte accesses maybe we can just do: if (xlen & 0x3) { .. do one byte .. xlen -= 1; } else { .. existing 32 bit code .. } but I guess we need to handle unaligned accesses as well. Florian, Can you help clarify what the datasheet means here? Thanks, <snip> >> rpi kernel also goes to efforts to not write sub-4 byte lengths so >> lets: -- Alex Bennée Virtualisation Tech Lead @ Linaro
