From: Yang Weijiang <[email protected]> CET provides a new architectural register, shadow stack pointer (SSP), which cannot be directly encoded as a source, destination or memory operand in instructions. But Intel VMCS & VMCB provide fields to save/load guest & host's ssp.
It's necessary to save & restore Guest's ssp before & after migration. To support this, KVM implements Guest's SSP as a special KVM internal register - KVM_REG_GUEST_SSP, and allows QEMU to save & load it via KVM_GET_ONE_REG/KVM_SET_ONE_REG. Cache KVM_REG_GUEST_SSP in X86CPUState. Tested-by: Farrah Chen <[email protected]> Reviewed-by: Xiaoyao Li <[email protected]> Signed-off-by: Yang Weijiang <[email protected]> Co-developed-by: Chao Gao <[email protected]> Signed-off-by: Chao Gao <[email protected]> Co-developed-by: Zhao Liu <[email protected]> Signed-off-by: Zhao Liu <[email protected]> --- target/i386/cpu.h | 3 ++- target/i386/kvm/kvm.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 661b798da4d0..c4412012c780 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1982,7 +1982,7 @@ typedef struct CPUArchState { uint64_t fred_config; #endif - /* CET MSRs */ + /* CET MSRs and register */ uint64_t u_cet; uint64_t s_cet; uint64_t pl0_ssp; /* also used for FRED */ @@ -1992,6 +1992,7 @@ typedef struct CPUArchState { #ifdef TARGET_X86_64 uint64_t int_ssp_table; #endif + uint64_t guest_ssp; uint64_t tsc_adjust; uint64_t tsc_deadline; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4eb58ca19d79..1ebe20f7fb57 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4292,6 +4292,35 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) return kvm_buf_set_msrs(cpu); } +static int kvm_put_kvm_regs(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + int ret; + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + ret = kvm_set_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SSP), + &env->guest_ssp); + if (ret) { + return ret; + } + } + return 0; +} + +static int kvm_get_kvm_regs(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + int ret; + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + ret = kvm_get_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SSP), + &env->guest_ssp); + if (ret) { + return ret; + } + } + return 0; +} static int kvm_get_xsave(X86CPU *cpu) { @@ -5445,6 +5474,11 @@ int kvm_arch_put_registers(CPUState *cpu, KvmPutState level, Error **errp) error_setg_errno(errp, -ret, "Failed to set MSRs"); return ret; } + ret = kvm_put_kvm_regs(x86_cpu); + if (ret < 0) { + error_setg_errno(errp, -ret, "Failed to set KVM type registers"); + return ret; + } ret = kvm_put_vcpu_events(x86_cpu, level); if (ret < 0) { error_setg_errno(errp, -ret, "Failed to set vCPU events"); @@ -5517,6 +5551,11 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp) error_setg_errno(errp, -ret, "Failed to get MSRs"); goto out; } + ret = kvm_get_kvm_regs(cpu); + if (ret < 0) { + error_setg_errno(errp, -ret, "Failed to get KVM type registers"); + goto out; + } ret = kvm_get_apic(cpu); if (ret < 0) { error_setg_errno(errp, -ret, "Failed to get APIC"); -- 2.34.1
