Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max,
then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change
of ASID still causes a TLB flush.
Changes since V5:
- Patch 2:
- More specific TLB flush. Now only flushes the TLBs relevant to the
written register, and then only if A2 changes.
Thanks to Richard Henderson for advice on TLB flushing.
Signed-off-by: Jim MacArthur <[email protected]>
---
Jim MacArthur (4):
target/arm: Enable ID_AA64MMFR4_EL1 register
target/arm: Allow writes to FNG1, FNG0, A2
target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
tests: Add test for ASID2 and write/read of feature bits
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 7 ++++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/helper.c | 32 ++++++++++++-----
target/arm/internals.h | 5 +++
target/arm/tcg/cpu64.c | 4 +++
tests/tcg/aarch64/system/asid2.c | 76 ++++++++++++++++++++++++++++++++++++++++
7 files changed, 118 insertions(+), 8 deletions(-)
---
base-commit: 9c23f2a7b0b45277693a14074b1aaa827eecdb92
change-id: 20251210-jmac-asid2-a82ba351478d
Best regards,
--
Jim MacArthur <[email protected]>
