On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <[email protected]> wrote: > > From: Kane-Chen-AS <[email protected]> > > Connect the AST1700 device as a child of the AST27X0 model to reflect > its role in DC-SCM 2.0 LTPI-based architectures. This patch wires > the AST1700 device into the platform without introducing functional > peripherals. > > This forms the base for LTPI expander emulation in QEMU using > AST27X0 as the host controller. > > Note: ioexp_num is set to 0 at this stage. Once all related devices > and interrupts are fully implemented, ioexp_num will be updated to > its expected value. This ensures the machine remains functional at > every commit and avoids potential compiler or build issues. > > Signed-off-by: Kane-Chen-AS <[email protected]> > Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Nabih Estefan <[email protected]> Tested-by: Nabih Estefan <[email protected]> > --- > include/hw/arm/aspeed_soc.h | 7 +++++-- > hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++-------- > 2 files changed, 23 insertions(+), 10 deletions(-) > > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index 7b08cca908..f19bab3457 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -45,6 +45,7 @@ > #include "hw/char/serial-mm.h" > #include "hw/intc/arm_gicv3.h" > #include "hw/misc/aspeed_ltpi.h" > +#include "hw/arm/aspeed_ast1700.h" > > #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" > > @@ -112,10 +113,10 @@ struct AspeedSoCState { > UnimplementedDeviceState dpmcu; > UnimplementedDeviceState espi; > UnimplementedDeviceState udc; > - UnimplementedDeviceState ltpi; > UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; > AspeedAPB2OPBState fsi[2]; > AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; > + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; > }; > > #define TYPE_ASPEED_SOC "aspeed-soc" > @@ -178,6 +179,7 @@ struct AspeedSoCClass { > int macs_num; > int uarts_num; > int uarts_base; > + int ioexp_num; > const int *irqmap; > const hwaddr *memmap; > uint32_t num_cpus; > @@ -190,7 +192,6 @@ enum { > ASPEED_DEV_IOMEM, > ASPEED_DEV_IOMEM0, > ASPEED_DEV_IOMEM1, > - ASPEED_DEV_LTPI, > ASPEED_DEV_UART0, > ASPEED_DEV_UART1, > ASPEED_DEV_UART2, > @@ -285,6 +286,8 @@ enum { > ASPEED_DEV_IPC1, > ASPEED_DEV_LTPI_CTRL1, > ASPEED_DEV_LTPI_CTRL2, > + ASPEED_DEV_LTPI_IO0, > + ASPEED_DEV_LTPI_IO1, > }; > > const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 341b53189b..de39a3e7eb 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -26,7 +26,6 @@ > #define AST2700_SOC_IO_SIZE 0x00FE0000 > #define AST2700_SOC_IOMEM_SIZE 0x01000000 > #define AST2700_SOC_DPMCU_SIZE 0x00040000 > -#define AST2700_SOC_LTPI_SIZE 0x01000000 > > static const hwaddr aspeed_soc_ast2700_memmap[] = { > [ASPEED_DEV_VBOOTROM] = 0x00000000, > @@ -91,7 +90,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { > [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000, > [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000, > [ASPEED_DEV_WDT] = 0x14C37000, > - [ASPEED_DEV_LTPI] = 0x30000000, > + [ASPEED_DEV_LTPI_IO0] = 0x30000000, > + [ASPEED_DEV_LTPI_IO1] = 0x50000000, > [ASPEED_DEV_PCIE_MMIO0] = 0x60000000, > [ASPEED_DEV_PCIE_MMIO1] = 0x80000000, > [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000, > @@ -563,10 +563,14 @@ static void aspeed_soc_ast2700_init(Object *obj) > &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); > } > > + for (i = 0; i < sc->ioexp_num; i++) { > + /* AST1700 IOEXP */ > + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], > + TYPE_ASPEED_AST1700); > + } > + > object_initialize_child(obj, "dpmcu", &s->dpmcu, > TYPE_UNIMPLEMENTED_DEVICE); > - object_initialize_child(obj, "ltpi", &s->ltpi, > - TYPE_UNIMPLEMENTED_DEVICE); > object_initialize_child(obj, "iomem", &s->iomem, > TYPE_UNIMPLEMENTED_DEVICE); > object_initialize_child(obj, "iomem0", &s->iomem0, > @@ -1068,14 +1072,19 @@ static void aspeed_soc_ast2700_realize(DeviceState > *dev, Error **errp) > aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); > } > > + /* IO Expander */ > + for (i = 0; i < sc->ioexp_num; i++) { > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, > + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); > + } > + > aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), > "aspeed.dpmcu", > sc->memmap[ASPEED_DEV_DPMCU], > AST2700_SOC_DPMCU_SIZE); > - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), > - "aspeed.ltpi", > - sc->memmap[ASPEED_DEV_LTPI], > - AST2700_SOC_LTPI_SIZE); > aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), > "aspeed.io", > sc->memmap[ASPEED_DEV_IOMEM], > @@ -1143,6 +1152,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass > *oc, const void *data) > sc->macs_num = 3; > sc->uarts_num = 13; > sc->num_cpus = 4; > + sc->ioexp_num = 0; > sc->uarts_base = ASPEED_DEV_UART0; > sc->irqmap = aspeed_soc_ast2700a1_irqmap; > sc->memmap = aspeed_soc_ast2700_memmap; > -- > 2.43.0 >
