Hi Philippe,
On 12/26/25 17:06, Philippe Mathieu-Daudé wrote:
> Hi Frédéric,
>
> On 16/12/25 22:24, Frédéric Pétrot wrote:
>> The lq and sq helpers for the experimental rv128 architecture currently
>> use direct (and erroneous) memory accesses.
>> Replace these direct accesses with the standard tcg_gen_qemu_{ld,st}_i128
>> TCG helpers that handle endianness issues.
>>
>> Reported-by: Philippe Mathieu-Daudé <[email protected]>
>> Suggested-by: Richard Henderson <[email protected]>
>> Signed-off-by: Frédéric Pétrot <[email protected]>
>
> Errors when building qemu-system-riscv32:
>
> [3/5] Compiling C object
> libqemu-riscv32-softmmu.a.p/target_riscv_translate.c.o
> In file included from ../../target/riscv/translate.c:1192:
> ../../target/riscv/insn_trans/trans_rvi.c.inc:395:35: error: incompatible
> pointer types passing 'TCGv' (aka 'struct TCGv_i32_d *') to parameter of type
> 'TCGv_i64' (aka 'struct TCGv_i64_d *') [-Werror,-Wincompatible-pointer-types]
> 395 | tcg_gen_extr_i128_i64(destl, desth, t16);
> | ^~~~~
> include/tcg/tcg-op-common.h:309:37: note: passing argument to parameter 'lo'
> here
> 309 | void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg);
> | ^~
> ...
Outch, sorry for that!
Since lq/sq are meaningful only for x-rv128 that is based on rv64, I've
handled this compilation issue in such a way that it compiles for rv32
and compiles and does what is expected for rv64 with '-cpu x-rv128'.
Using these 128-bit ld/st has the additional benefit of allowing the use
of the mttcg, as, if I understood correctly, they are atomic.
Frédéric Pétrot (2):
trans_rvi.c.inc: Make lq and sq use 128-bit ld/st
riscv/tcg/tcg-cpu.c: Remove smp check for x-rv128
target/riscv/insn_trans/trans_rvi.c.inc | 32 ++++++++++++++++++-------
target/riscv/tcg/tcg-cpu.c | 10 --------
2 files changed, 24 insertions(+), 18 deletions(-)
--
2.43.0
