We had to check that mttcg was not used when executing QEMU with -cpu x-rv128 as a single 128-bit access was done as two distinct 64-bit accesses. Now that we use the 128-bit ld/st that access the data atomically, this check is no longer necessary.
Signed-off-by: Frédéric Pétrot <[email protected]> --- target/riscv/tcg/tcg-cpu.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 440626ddfa..15d39f9912 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) } #ifndef CONFIG_USER_ONLY - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - - if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { - /* Missing 128-bit aligned atomics */ - error_setg(errp, - "128-bit RISC-V currently does not work with Multi " - "Threaded TCG. Please use: -accel tcg,thread=single"); - return false; - } - CPURISCVState *env = &cpu->env; tcg_cflags_set(CPU(cs), CF_PCREL); -- 2.43.0
