> Subject: [PATCH 10/19] hw/i3c/dw-i3c: Use 32 bits on MMIO writes > > The registers are only 32 bits wide, so we should cast the 64-bit value > passed in > to only be 32 bits wide. > > Signed-off-by: Joe Komlodi <[email protected]> > > Reviewed-by: Patrick Venture <[email protected]> > Reviewed-by: Titus Rwantare <[email protected]> > --- > hw/i3c/dw-i3c.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index bf51c00935..ecd79aba8c > 100644 > --- a/hw/i3c/dw-i3c.c > +++ b/hw/i3c/dw-i3c.c > @@ -380,10 +380,11 @@ static void dw_i3c_write(void *opaque, hwaddr > offset, uint64_t value, { > DWI3C *s = DW_I3C(opaque); > uint32_t addr = offset >> 2; > + uint32_t val32 = (uint32_t)value; > > trace_dw_i3c_write(s->id, offset, value); > > - value &= ~dw_i3c_ro[addr]; > + val32 &= ~dw_i3c_ro[addr]; > switch (addr) { > case R_HW_CAPABILITY: > case R_RESPONSE_QUEUE_PORT: > @@ -409,7 +410,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, > uint64_t value, > case R_RESET_CTRL: > break; > default: > - s->regs[addr] = value; > + s->regs[addr] = val32; > break; > } > } > -- > 2.50.0.rc1.591.g9c95f17f64-goog
Reviewed-by: Jamin Lin <[email protected]> Thanks, Jamin
