This patch series adds Zvqdotq support. The isa spec of Zvqdotq extension is not ratified yet, so this patch series is based on the latest draft of the spec (v0.0.2) and make the Zvqdotq extension as an experimental extension.
The draft of the Zvqdotq isa spec: https://github.com/riscv/riscv-dot-product v5: * Add disassembler support * Rebase to riscv-to-apply.next branch v4: * Update the PRIV_VERSION (Thanks for Daniel Henrique Barboza's * suggestion) v3: * Fix casting and simplify vs1/vs2 access (Thanks for Richard * Henderson's suggestion) v2: * Remove unnecessary variable and mask (Thanks for Richard Henderson's suggestion) Max Chou (4): target/riscv: Add Zvqdotq cfg property target/riscv: rvv: Add Zvqdotq support target/riscv: Expose Zvqdotq extension as a cpu property disas/riscv: Support the Zvqdotq extension disas/riscv.c | 21 +++++++ target/riscv/cpu.c | 2 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvzvqdotq.c.inc | 61 +++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 ++ target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 57 +++++++++++++++++ 9 files changed, 167 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvqdotq.c.inc -- 2.43.7
