The Zvqdotq provides following instructions: - vqdot.[vv,vx] Vector 8-bit Signed-Signed Dot Product - vqdotu.[vv,vx] Vector 8-bit Unsigned Dot Product - vqdotsu.[vv,vx] Vector 8-bit Signed-Unsigned Dot Product - vqdotus.vx Vector 8-bit Unsigned-Signed Dot Product
Signed-off-by: Max Chou <[email protected]> --- disas/riscv.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 85cd2a9c2a..b7520f2b42 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -984,6 +984,13 @@ typedef enum { rv_op_ssamoswap_d = 953, rv_op_c_sspush = 954, rv_op_c_sspopchk = 955, + rv_op_vqdot_vv = 956, + rv_op_vqdot_vx = 957, + rv_op_vqdotu_vv = 958, + rv_op_vqdotu_vx = 959, + rv_op_vqdotsu_vv = 960, + rv_op_vqdotsu_vx = 961, + rv_op_vqdotus_vx = 962, } rv_op; /* register names */ @@ -2254,6 +2261,13 @@ const rv_opcode_data rvi_opcode_data[] = { rv_op_sspush, 0 }, { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, rv_op_sspopchk, 0 }, + { "vqdot.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdot.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdotu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdotu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdotsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdotsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, + { "vqdotus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, }; /* CSR names */ @@ -3738,8 +3752,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 37: op = rv_op_vmul_vv; break; case 38: op = rv_op_vmulhsu_vv; break; case 39: op = rv_op_vmulh_vv; break; + case 40: op = rv_op_vqdotu_vv; break; case 41: op = rv_op_vmadd_vv; break; + case 42: op = rv_op_vqdotsu_vv; break; case 43: op = rv_op_vnmsub_vv; break; + case 44: op = rv_op_vqdot_vv; break; case 45: op = rv_op_vmacc_vv; break; case 47: op = rv_op_vnmsac_vv; break; case 48: op = rv_op_vwaddu_vv; break; @@ -3945,9 +3962,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 37: op = rv_op_vmul_vx; break; case 38: op = rv_op_vmulhsu_vx; break; case 39: op = rv_op_vmulh_vx; break; + case 40: op = rv_op_vqdotu_vx; break; case 41: op = rv_op_vmadd_vx; break; + case 42: op = rv_op_vqdotsu_vx; break; case 43: op = rv_op_vnmsub_vx; break; + case 44: op = rv_op_vqdot_vx; break; case 45: op = rv_op_vmacc_vx; break; + case 46: op = rv_op_vqdotus_vx; break; case 47: op = rv_op_vnmsac_vx; break; case 48: op = rv_op_vwaddu_vx; break; case 49: op = rv_op_vwadd_vx; break; -- 2.43.7
