On Wed, 10 Dec 2025 at 14:51, Jim MacArthur <[email protected]> wrote:
>
> Reviewed-by: Richard Henderson <[email protected]>
> Reviewed-by: Alex Bennée <[email protected]>
> Reviewed-by: Gustavo Romero <[email protected]>
> Signed-off-by: Jim MacArthur <[email protected]>
> ---
> target/arm/cpu-sysregs.h.inc | 1 +
> target/arm/helper.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index 2bb2861c62..2ba49d8478 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
> DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
> DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
> DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
> DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 27ebc6f29b..c20334fa65 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) },
> - { .name = "ID_AA64MMFR4_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = 0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) },
> { .name = "ID_AA64MMFR5_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
This needs a small extra bit:
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6706,6 +6706,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.exported_bits = R_ID_AA64MMFR2_AT_MASK },
{ .name = "ID_AA64MMFR3_EL1",
.exported_bits = 0 },
+ { .name = "ID_AA64MMFR4_EL1",
+ .exported_bits = 0 },
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
.is_glob = true },
{ .name = "ID_AA64DFR0_EL1",
This is where we tell the user-mode emulator what parts of the ID
register it should expose to the guest process. For ID_AA64MMFR4_EL1
that is nothing (i.e. read-as-zero) because no relevant fields
are listed here:
https://docs.kernel.org/arch/arm64/cpu-feature-registers.html
But we need an entry for it here, because changing the name from
"ID_AA64MMFR4_EL1_RESERVED" means it no longer matches the glob
pattern in the "ID_AA64MMFR*_EL1_RESERVED" catch-all entry
(which also says "make it read-as-zero").
This is a trivial fix so I'll just apply it when I take this
into target-arm.next rather than requiring you to do a respin.
thanks
-- PMM
