On Wed, 10 Dec 2025 at 14:51, Jim MacArthur <[email protected]> wrote: > > Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max, > then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change > of ASID still causes a TLB flush. > > Changes since V5: > > - Patch 2: > - More specific TLB flush. Now only flushes the TLBs relevant to the > written register, and then only if A2 changes. > > Thanks to Richard Henderson for advice on TLB flushing. > > Signed-off-by: Jim MacArthur <[email protected]> > --- > Jim MacArthur (4): > target/arm: Enable ID_AA64MMFR4_EL1 register > target/arm: Allow writes to FNG1, FNG0, A2 > target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max > tests: Add test for ASID2 and write/read of feature bits
Applied to target-arm.next with the minor fixup on patch 1; thanks. -- PMM
