On Sun, 11 Jan 2026 19:53:16 +0000 Shameer Kolothum <[email protected]> wrote:
> QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits. > With accelerator mode enabled, a device may use SVA, where CPU page tables > are shared with the SMMU, requiring an OAS at least as large as the > CPU’s output address size. A user option is added to configure this. > > However, the OAS value advertised by the virtual SMMU must remain > compatible with the capabilities of the host SMMUv3. In accelerated > mode, the host SMMU performs stage-2 translation and must be able to > consume the intermediate physical addresses (IPA) produced by stage-1. > > The OAS exposed by the virtual SMMU defines the maximum IPA width that > stage-1 translations may generate. For AArch64 implementations, the > maximum usable IPA size on the host SMMU is determined by its own OAS. > Check that the configured OAS does not exceed what the host SMMU > can safely support. > > Tested-by: Zhangfei Gao <[email protected]> > Reviewed-by: Nicolin Chen <[email protected]> > Reviewed-by: Eric Auger <[email protected]> > Signed-off-by: Shameer Kolothum <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]>
