On Mon, 12 Jan 2026 at 03:55, Shameer Kolothum <[email protected]> wrote: > > Hi, > > Major changes since v6: > > https://lore.kernel.org/qemu-devel/[email protected]/ > > - Addressed feedback from v6 and picked up R-by tags. Thanks! > - Fixed build and compilation issues reported on multiple architectures. > - Reworked and introduced a HostIOMMUDeviceClass callback to retrieve > pasid info(patch #32) > - Added an helper to insert a CAP ID at an offset in PCIe config space > (patch #33) > - Added an x-vpasid-cap-offset property for vfio-pci devices to allow > opt-in synthesis of the PASID capability (patch #35). > - Renamed the pasid property to ssidsize (patch #36). > - VFIO/IOMMUFD changes depend on Zhenzhong’s pass-through support series, > patches 4/5/8 [0]. > > Patch organization: > > 1–27: Enable accelerated SMMUv3 with features aligned to the default QEMU > SMMUv3 implementation, including IORT RMR-based MSI support. > > 28–30: Add user-configurable options for RIL, ATS, and OAS features. > > 31–36: Add PASID support, including required VFIO changes. > > Testing: > Basic sanity testing was performed on an NVIDIA Grace platform with GPU > device assignment. A CUDA test application was used to validate the SVA > use case. Additional testing and feedback are welcome. > > Eg: Qemu Cmd line: > > qemu-system-aarch64 -machine virt,gic-version=3,highmem-mmio-size=2T \ > -cpu host -smp cpus=4 -m size=16G,slots=2,maxmem=66G -nographic \ > -bios QEMU_EFI.fd -object iommufd,id=iommufd0 -enable-kvm \ > -object memory-backend-ram,size=8G,id=m0 \ > -object memory-backend-ram,size=8G,id=m1 \ > -numa node,memdev=m0,cpus=0-3,nodeid=0 -numa node,memdev=m1,nodeid=1 \ > -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 -numa > node,nodeid=5 \ > -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 -numa > node,nodeid=9 \ > -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0 \ > -device > arm-smmuv3,primary-bus=pcie.1,id=smmuv3.0,accel=on,ats=on,ril=off,ssidsize=20,oas=48 > \ > -device > pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,pref64-reserve=512G,id=dev0 > \ > -device > vfio-pci,host=0019:06:00.0,rombar=0,id=dev0,iommufd=iommufd0,bus=pcie.port1,x-vpasid-cap-offset=0xff8 > \ > -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=2 \ > ... > -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=9 \ > -device pxb-pcie,id=pcie.2,bus_nr=8,bus=pcie.0 \ > -device > arm-smmuv3,primary-bus=pcie.2,id=smmuv3.1,accel=on,ats=on,ril=off,ssidsize=20,oas=48 > \ > -device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2,pref64-reserve=512G > \ > -device > vfio-pci,host=0018:06:00.0,rombar=0,id=dev1,iommufd=iommufd0,bus=pcie.port2,x-vpasid-cap-offset=0xff8 > \ > -device virtio-blk-device,drive=fs \ > -drive file=image.qcow2,index=0,media=disk,format=qcow2,if=none,id=fs \ > -net none \ > -nographic > > A complete branch can be found here, > https://github.com/shamiali2008/qemu-master/tree/master-smmuv3-accel-v7-ext > > Please take a look and let me know your feedback.
Thanks Shameer The whole series is tested well with Shameer's fix of patch 33. Tested-by: Zhangfei Gao <[email protected]> https://github.com/Linaro/qemu/tree/master-smmuv3-accel-v7 Thanks
