v2 separates out prep patches so the machine can be reviewed independently. It depends on the following two series:
AIA: https://lore.kernel.org/qemu-devel/[email protected] Boot: https://lore.kernel.org/qemu-devel/[email protected] Original cover letter: Introducing Tenstorrent Atlantis! The Tenstorrent Atlantis platform is a collaboration between Tenstorrent and CoreLab Technology. It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. This initial series adds the base machine support including: - AIA (Advanced Interrupt Architecture) support - PCIe controller and DesignWare I2C integration - Serial console and device tree generation - Functional tests for OpenSBI+Linux boot Based-on: [email protected] [email protected] Joel Stanley (3): hw/riscv: Add Tenstorrent Atlantis machine hw/riscv/atlantis: Integrate i2c buses hw/riscv/atlantis: Add some i2c peripherals Nicholas Piggin (3): hw/riscv/atlantis: Add PCIe controller tests/functional/riscv64: Add tt-atlantis tests hw/riscv/atlantis: Use halting kernel if there is no payload MAINTAINERS | 9 + docs/system/riscv/tt_atlantis.rst | 38 + docs/system/target-riscv.rst | 1 + include/hw/riscv/tt_atlantis.h | 94 ++ hw/riscv/tt_atlantis.c | 916 +++++++++++++++++++ hw/riscv/Kconfig | 21 + hw/riscv/meson.build | 1 + tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_tt_atlantis.py | 68 ++ 10 files changed, 1153 insertions(+) create mode 100644 docs/system/riscv/tt_atlantis.rst create mode 100644 include/hw/riscv/tt_atlantis.h create mode 100644 hw/riscv/tt_atlantis.c create mode 100755 tests/functional/riscv64/test_tt_atlantis.py -- 2.47.3
