On 12/27/25 00:37, Laurent Vivier wrote:
According to Programmer's Reference Manual, if Dc1 and Dc2 specify the same data register and the comparison fails, memory operand 1 is stored in the data register.The current helpers wrote Dc1 then Dc2, leaving operand 2 in the shared register. Swap the writeback order for cas2w/cas2l so memory operand 1 wins.
This seems to be a qemu-stable material, I'm picking it up. Please let me know if I shouldn't. Thanks, /mjt
