On 1/15/26 22:33, Paolo Bonzini wrote:
32-bit TCG opcodes produced for the i386 target usually looks the same
as 64-bit TCG opcodes produced for the x86_64. The special one that
needs extensions is 32-bit TCG opcodes produced for the x86_64 target.
Make all #ifdefs look the same, like this:
case MO_32:
#ifdef TARGET_X86_64
/* code using 32-bit opcodes */
case MO_64:
#endif
/* code using target_long opcodes */
default:
g_assert_not_reached();
Signed-off-by: Paolo Bonzini <[email protected]>
---
target/i386/tcg/translate.c | 11 ++++++-----
target/i386/tcg/emit.c.inc | 18 ++++++++++++------
2 files changed, 18 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <[email protected]>
case MO_32:
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a mov. */
+#ifdef TARGET_X86_64
dest = dest ? dest : cpu_regs[reg];
tcg_gen_ext32u_tl(dest, t0);
break;
-#ifdef TARGET_X86_64
case MO_64:
+#endif
dest = dest ? dest : cpu_regs[reg];
tcg_gen_mov_tl(dest, t0);
break;
-#endif
default:
g_assert_not_reached();
}
This could plausibly share the dest selection code and then use
tcg_gen_ext_tl(dest, t0, mop).
@@ -1236,8 +1236,8 @@ static void gen_ADCOX(DisasContext *s, X86DecodedInsn
*decode, int cc_op)
...
+ case MO_64:
#endif
- default:
zero = tcg_constant_tl(0);
tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero);
tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero);
break;
A fairly new function, but this could use
tcg_gen_addcio_tl(s->T0, *carry_out, s->T0, s->T1, carry_in);
r~
