Implement the IRS frame ID registers IRS_IDR[0-7], IRS_IIDR and IRS_AIDR. These are all 32-bit registers.
We make these fields in the GIC state struct rather than just hardcoding them in the register read function so that we can later code "do this only if X is implemented" as a test on the ID register value. Signed-off-by: Peter Maydell <[email protected]> --- hw/intc/arm_gicv5.c | 112 +++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 39 ++++++++++ 2 files changed, 151 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index db754e7681..f34bb81966 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -268,6 +268,62 @@ REG64(IRS_SWERR_SYNDROMER1, 0x3d0) static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + GICv5Common *cs = ARM_GICV5_COMMON(s); + uint32_t v = 0; + + switch (offset) { + case A_IRS_IDR0: + v = cs->irs_idr0; + /* INT_DOM reports the domain this register is for */ + v = FIELD_DP32(v, IRS_IDR0, INT_DOM, domain); + if (domain != GICV5_ID_REALM) { + /* MEC field RES0 except for the Realm domain */ + v &= ~R_IRS_IDR0_MEC_MASK; + } + if (domain == GICV5_ID_EL3) { + /* VIRT is RES0 for EL3 domain */ + v &= ~R_IRS_IDR0_VIRT_MASK; + } + return true; + + case A_IRS_IDR1: + *data = cs->irs_idr1; + return true; + + case A_IRS_IDR2: + *data = cs->irs_idr2; + return true; + + case A_IRS_IDR3: + /* In EL3 IDR0.VIRT is 0 so this is RES0 */ + *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr3; + return true; + + case A_IRS_IDR4: + /* In EL3 IDR0.VIRT is 0 so this is RES0 */ + *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr4; + return true; + + case A_IRS_IDR5: + *data = cs->irs_idr5; + return true; + + case A_IRS_IDR6: + *data = cs->irs_idr6; + return true; + + case A_IRS_IDR7: + *data = cs->irs_idr7; + return true; + + case A_IRS_IIDR: + *data = cs->irs_iidr; + return true; + + case A_IRS_AIDR: + *data = cs->irs_aidr; + return true; + } return false; } @@ -443,6 +499,60 @@ static void gicv5_reset_hold(Object *obj, ResetType type) } } +static void gicv5_set_idregs(GICv5Common *cs) +{ + /* Set the ID register value fields */ + uint32_t v; + + /* + * We don't support any of the optional parts of the spec currently, + * so most of the fields in IRS_IDR0 are zero. + */ + v = 0; + /* + * We can handle physical addresses of any size, so report + * support for 56 bits of physical address space. + */ + v = FIELD_DP32(v, IRS_IDR0, PA_RANGE, 7); + v = FIELD_DP32(v, IRS_IDR0, IRSID, cs->irsid); + cs->irs_idr0 = v; + + v = 0; + v = FIELD_DP32(v, IRS_IDR1, PE_CNT, cs->num_cpus); + v = FIELD_DP32(v, IRS_IDR1, IAFFID_BITS, QEMU_GICV5_IAFFID_BITS - 1); + v = FIELD_DP32(v, IRS_IDR1, PRI_BITS, QEMU_GICV5_PRI_BITS - 1); + cs->irs_idr1 = v; + + v = 0; + /* We always support physical LPIs with 2-level ISTs of all sizes */ + v = FIELD_DP32(v, IRS_IDR2, ID_BITS, QEMU_GICV5_ID_BITS); + v = FIELD_DP32(v, IRS_IDR2, LPI, 1); + v = FIELD_DP32(v, IRS_IDR2, MIN_LPI_ID_BITS, QEMU_GICV5_MIN_LPI_ID_BITS); + v = FIELD_DP32(v, IRS_IDR2, IST_LEVELS, 1); + v = FIELD_DP32(v, IRS_IDR2, IST_L2SZ, 7); + /* Our impl does not need IST metadata, so ISTMD and ISTMD_SZ are 0 */ + cs->irs_idr2 = v; + + /* We don't implement virtualization yet, so these are zero */ + cs->irs_idr3 = 0; + cs->irs_idr4 = 0; + + /* These three have just one field each */ + cs->irs_idr5 = FIELD_DP32(0, IRS_IDR5, SPI_RANGE, cs->spi_range); + cs->irs_idr6 = FIELD_DP32(0, IRS_IDR6, SPI_IRS_RANGE, cs->spi_irs_range); + cs->irs_idr7 = FIELD_DP32(0, IRS_IDR7, SPI_BASE, cs->spi_base); + + v = 0; + v = FIELD_DP32(v, IRS_IIDR, IMPLEMENTER, QEMU_GICV5_IMPLEMENTER); + v = FIELD_DP32(v, IRS_IIDR, REVISION, QEMU_GICV5_REVISION); + v = FIELD_DP32(v, IRS_IIDR, VARIANT, QEMU_GICV5_VARIANT); + v = FIELD_DP32(v, IRS_IIDR, PRODUCTID, QEMU_GICV5_PRODUCTID); + cs->irs_iidr = v; + + /* This is a GICv5.0 IRS, so all fields are zero */ + cs->irs_aidr = 0; +} + static void gicv5_realize(DeviceState *dev, Error **errp) { GICv5Common *cs = ARM_GICV5_COMMON(dev); @@ -469,6 +579,8 @@ static void gicv5_realize(DeviceState *dev, Error **errp) * NS domain. */ cs->implemented_domains = (1 << GICV5_ID_NS); + + gicv5_set_idregs(cs); gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops); } diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h index be898abcd5..bcf7cd4239 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -65,6 +65,18 @@ struct GICv5Common { /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; + /* ID register values: set at realize, constant thereafter */ + uint32_t irs_idr0; + uint32_t irs_idr1; + uint32_t irs_idr2; + uint32_t irs_idr3; + uint32_t irs_idr4; + uint32_t irs_idr5; + uint32_t irs_idr6; + uint32_t irs_idr7; + uint32_t irs_iidr; + uint32_t irs_aidr; + /* Properties */ uint32_t num_cpus; ARMCPU **cpus; @@ -84,6 +96,33 @@ struct GICv5CommonClass { #define IRS_CONFIG_FRAME_SIZE 0x10000 +/* + * The architecture allows a GICv5 to implement less than the + * full width for various ID fields. QEMU's implementation + * always supports the full width of these fields. These constants + * define our implementation's limits. + */ + +/* Number of INTID.ID bits we support */ +#define QEMU_GICV5_ID_BITS 24 +/* Min LPI_ID_BITS supported */ +#define QEMU_GICV5_MIN_LPI_ID_BITS 14 +/* IAFFID bits supported */ +#define QEMU_GICV5_IAFFID_BITS 16 +/* Number of priority bits supported in the IRS */ +#define QEMU_GICV5_PRI_BITS 5 + +/* + * There are no TRMs currently published for hardware + * implementations of GICv5 that we might identify ourselves + * as. Instead, we borrow the Arm Implementer code and + * pick an arbitrary product ID (ASCII "Q") + */ +#define QEMU_GICV5_IMPLEMENTER 0x43b +#define QEMU_GICV5_PRODUCTID 0x51 +#define QEMU_GICV5_REVISION 0 +#define QEMU_GICV5_VARIANT 0 + /** * gicv5_common_init_irqs_and_mmio: Create IRQs and MMIO regions for the GICv5 * @s: GIC object -- 2.43.0
