ICC_IDR0_EL1 is an identification register; we can implement this as a simple constant value.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index c591e249b1..36d1c196a8 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -38,6 +38,18 @@ FIELD(GIC_CDHM, HM, 32, 1) FIELD(GIC_CDRCFG, ID, 0, 24) FIELD(GIC_CDRCFG, TYPE, 29, 3) +FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4) +FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4) +FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) + +/* + * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, + * and no legacy GICv3.3 vcpu interface (yet) + */ +#define QEMU_ICC_IDR0 \ + ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \ + (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT)) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -220,6 +232,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, .writefn = gic_cdhm_write, }, + { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2, + .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue = QEMU_ICC_IDR0, + }, { .name = "ICC_ICSR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4, .access = PL1_RW, .type = ARM_CP_NO_RAW, -- 2.43.0
