In order to avoid symbol name clash when building a single binary, rename TCG helpers prefixing with the target name.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/arm/tcg/helper-defs.h | 4 ++-- target/i386/ops_sse.h | 2 +- target/loongarch/tcg/helper.h | 4 ++-- target/mips/helper.h | 4 ++-- target/i386/tcg/ops_sse_header.h.inc | 2 +- target/arm/tcg/arith_helper.c | 4 ++-- target/arm/tcg/translate.c | 4 ++-- target/loongarch/tcg/op_helper.c | 4 ++-- target/mips/tcg/op_helper.c | 4 ++-- target/mips/tcg/translate.c | 4 ++-- target/i386/tcg/emit.c.inc | 2 +- .../loongarch/tcg/insn_trans/trans_extra.c.inc | 16 ++++++++-------- 12 files changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 5a10a9fba3b..a9e3583e2bb 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -493,8 +493,8 @@ DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) +DEF_HELPER_FLAGS_3(arm_crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) +DEF_HELPER_FLAGS_3(arm_crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index 99c4728ec81..3c683185253 100644 --- a/target/i386/ops_sse.h +++ b/target/i386/ops_sse.h @@ -2115,7 +2115,7 @@ void glue(helper_pcmpistrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, #define CRCPOLY 0x1edc6f41 #define CRCPOLY_BITREV 0x82f63b78 -target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len) +target_ulong helper_x86_crc32(uint32_t crc1, target_ulong msg, uint32_t len) { target_ulong crc = (msg & ((target_ulong) -1 >> (TARGET_LONG_BITS - len))) ^ crc1; diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index e36dd2f5de3..35b055eb3bc 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -12,8 +12,8 @@ DEF_HELPER_FLAGS_1(loongarch_bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl) -DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) +DEF_HELPER_FLAGS_3(loongarch_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) +DEF_HELPER_FLAGS_3(loongarch_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_2(cpucfg, TCG_CALL_NO_RWG_SE, tl, env, tl) /* Floating-point helper */ diff --git a/target/mips/helper.h b/target/mips/helper.h index 1c9f76f0c9c..e70a3942fac 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -21,8 +21,8 @@ DEF_HELPER_FLAGS_1(mips_bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif -DEF_HELPER_3(crc32, tl, tl, tl, i32) -DEF_HELPER_3(crc32c, tl, tl, tl, i32) +DEF_HELPER_3(mips_crc32, tl, tl, tl, i32) +DEF_HELPER_3(mips_crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) /* microMIPS functions */ diff --git a/target/i386/tcg/ops_sse_header.h.inc b/target/i386/tcg/ops_sse_header.h.inc index bbeb7301c33..8569f9935e3 100644 --- a/target/i386/tcg/ops_sse_header.h.inc +++ b/target/i386/tcg/ops_sse_header.h.inc @@ -337,7 +337,7 @@ DEF_HELPER_4(glue(pcmpestri, SUFFIX), void, env, Reg, Reg, i32) DEF_HELPER_4(glue(pcmpestrm, SUFFIX), void, env, Reg, Reg, i32) DEF_HELPER_4(glue(pcmpistri, SUFFIX), void, env, Reg, Reg, i32) DEF_HELPER_4(glue(pcmpistrm, SUFFIX), void, env, Reg, Reg, i32) -DEF_HELPER_3(crc32, tl, i32, tl, i32) +DEF_HELPER_3(x86_crc32, tl, i32, tl, i32) #endif /* AES-NI op helpers */ diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index cc081c8f966..3a5cb41c7a9 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -275,7 +275,7 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) * The upper bytes of val (above the number specified by 'bytes') must have * been zeroed out by the caller. */ -uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) +uint32_t HELPER(arm_crc32)(uint32_t acc, uint32_t val, uint32_t bytes) { uint8_t buf[4]; @@ -285,7 +285,7 @@ uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; } -uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) +uint32_t HELPER(arm_crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) { uint8_t buf[4]; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f9d1b8897d2..24cd316ee7a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3348,9 +3348,9 @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) } t3 = tcg_constant_i32(1 << sz); if (c) { - gen_helper_crc32c(t1, t1, t2, t3); + gen_helper_arm_crc32c(t1, t1, t2, t3); } else { - gen_helper_crc32(t1, t1, t2, t3); + gen_helper_arm_crc32(t1, t1, t2, t3); } store_reg(s, a->rd, t1); return true; diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c index 6b4fe535300..427b1da4004 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -60,7 +60,7 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) } } -target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz) +target_ulong helper_loongarch_crc32(target_ulong val, target_ulong m, uint64_t sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); @@ -70,7 +70,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz) return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); } -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz) +target_ulong helper_loongarch_crc32c(target_ulong val, target_ulong m, uint64_t sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 83c340e38e0..723253da59d 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -145,7 +145,7 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, } /* these crc32 functions are based on target/loongarch/tcg/op_helper.c */ -target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) +target_ulong helper_mips_crc32(target_ulong val, target_ulong m, uint32_t sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? @@ -157,7 +157,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); } -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz) +target_ulong helper_mips_crc32c(target_ulong val, target_ulong m, uint32_t sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index a63aa67808e..7ffa0d77273 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13440,9 +13440,9 @@ void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, gen_load_gpr(t1, rs); if (crc32c) { - gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz); + gen_helper_mips_crc32c(cpu_gpr[rd], t0, t1, tsz); } else { - gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz); + gen_helper_mips_crc32(cpu_gpr[rd], t0, t1, tsz); } } diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index ce636b6c56c..47b3940e943 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1916,7 +1916,7 @@ static void gen_CRC32(DisasContext *s, X86DecodedInsn *decode) TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(tmp, s->T0); - gen_helper_crc32(s->T0, tmp, s->T1, tcg_constant_i32(8 << ot)); + gen_helper_x86_crc32(s->T0, tmp, s->T1, tcg_constant_i32(8 << ot)); } static void gen_CVTPI2Px(DisasContext *s, X86DecodedInsn *decode) diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc b/target/loongarch/tcg/insn_trans/trans_extra.c.inc index 298a80cff55..0a45f6c16a2 100644 --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc @@ -101,11 +101,11 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a, return true; } -TRANS(crc_w_b_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) -TRANS(crc_w_h_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) -TRANS(crc_w_w_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) -TRANS64(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) -TRANS(crcc_w_b_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) -TRANS(crcc_w_h_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) -TRANS(crcc_w_w_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) -TRANS64(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) +TRANS(crc_w_b_w, CRC, gen_crc, gen_helper_loongarch_crc32, tcg_constant_tl(1)) +TRANS(crc_w_h_w, CRC, gen_crc, gen_helper_loongarch_crc32, tcg_constant_tl(2)) +TRANS(crc_w_w_w, CRC, gen_crc, gen_helper_loongarch_crc32, tcg_constant_tl(4)) +TRANS64(crc_w_d_w, CRC, gen_crc, gen_helper_loongarch_crc32, tcg_constant_tl(8)) +TRANS(crcc_w_b_w, CRC, gen_crc, gen_helper_loongarch_crc32c, tcg_constant_tl(1)) +TRANS(crcc_w_h_w, CRC, gen_crc, gen_helper_loongarch_crc32c, tcg_constant_tl(2)) +TRANS(crcc_w_w_w, CRC, gen_crc, gen_helper_loongarch_crc32c, tcg_constant_tl(4)) +TRANS64(crcc_w_d_w, CRC, gen_crc, gen_helper_loongarch_crc32c, tcg_constant_tl(8)) -- 2.52.0
