Hi Zhenzhong, I'm a bit confused about this patch.
All the other VTD_ECAP_* are masks for the ecap qword. The purpose of this new definition of ECAP_PSS differs a bit as it extracts the field itself :/ cmd ________________________________ From: Zhenzhong Duan <[email protected]> Sent: 14 February 2026 04:41 To: [email protected] <[email protected]> Cc: [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; CLEMENT MATHIEU--DRIF <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; Zhenzhong Duan <[email protected]> Subject: [RFCv2 PATCH 12/13] intel_iommu_accel: Add pasid bits size check Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. If pasid bits size is bigger than host side, host could fail to emulate all bindings in guest. Add a check to fail device plug early. Pasid bits size should also be no more than 20 bits according to PCI spec. Signed-off-by: Zhenzhong Duan <[email protected]> --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 5 +++++ hw/i386/intel_iommu_accel.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e4bcc884b0..e5518a94ea 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -195,6 +195,7 @@ #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_NWFS (1ULL << 33) +#define VTD_ECAP_PSS(x) extract64(x, 35, 5) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_PDS (1ULL << 42) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6483cb3d85..c1b31b17de 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5545,6 +5545,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) error_setg(errp, "Need to set scalable mode for PASID"); return false; } + if (s->pasid >= PCI_EXT_CAP_PASID_MAX_WIDTH) { + error_setg(errp, "PASID width %d, exceed Max PASID Width %d allowed " + "in PCI spec", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH); + return false; + } if (s->svm) { if (!x86_iommu->dt_supported) { diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index acb1b1e238..15412123d5 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -44,6 +44,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, HostIOMMUDevice *hiod = vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps = &hiod->caps; struct iommu_hw_info_vtd *vtd = &caps->vendor_caps.vtd; + uint8_t hpasid = VTD_ECAP_PSS(vtd->ecap_reg) + 1; PCIBus *bus = vtd_hiod->bus; PCIDevice *pdev = bus->devices[vtd_hiod->devfn]; @@ -64,6 +65,13 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, return false; } + /* Only do the check when host device support PASIDs */ + if (caps->max_pasid_log2 && s->pasid > hpasid) { + error_setg(errp, "PASID bits size %d > host IOMMU PASID bits size %d", + s->pasid, hpasid); + return false; + } + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { error_setg(errp, "Host device downstream to a PCI bridge is " "unsupported when x-flts=on"); -- 2.47.3
