Hi Zhenzhong, Maybe VTD_ECAP_PSS could be modified to take the pasid width and return the PSS field with the correct offset.
This comment echos what I said about [12/13] cmd ________________________________ From: Zhenzhong Duan <[email protected]> Sent: 14 February 2026 04:41 To: [email protected] <[email protected]> Cc: [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; CLEMENT MATHIEU--DRIF <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; [email protected] <[email protected]>; Zhenzhong Duan <[email protected]> Subject: [RFCv2 PATCH 05/13] intel_iommu: Change pasid property from bool to uint8 Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. 'x-pasid-mode' is a bool property, we need an extra 'pss' property to represent PASID size supported. Because there is no any device in QEMU supporting pasid capability yet, no guest could use the pasid feature until now, 'x-pasid-mode' takes no effect. So instead of an extra 'pss' property we can use a single 'pasid' property of uint8 type to represent if pasid is supported and the PASID bits size. A value of N > 0 means pasid is supported and N - 1 is the value in PSS field in ECAP register. Signed-off-by: Zhenzhong Duan <[email protected]> --- hw/i386/intel_iommu_internal.h | 1 - include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 4 ++-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 11a53aa369..04a9392e8a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -195,7 +195,6 @@ #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_NWFS (1ULL << 33) -#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */ #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_PDS (1ULL << 42) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 54c2b6b77a..bb957b93e0 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -315,7 +315,7 @@ struct IntelIOMMUState { OnOffAuto intr_eim; /* Toggle for EIM cabability */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ bool dma_drain; /* Whether DMA r/w draining enabled */ - bool pasid; /* Whether to support PASID */ + uint8_t pasid; /* PASID supported in bits, 0 if not */ bool fs1gp; /* First Stage 1-GByte Page Support */ /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 92a367d657..e27a7c725f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4186,7 +4186,7 @@ static const Property vtd_properties[] = { DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE), DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false), - DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), + DEFINE_PROP_UINT8("pasid", IntelIOMMUState, pasid, 0), DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), @@ -5033,7 +5033,7 @@ static void vtd_cap_init(IntelIOMMUState *s) } if (s->pasid) { - s->ecap |= VTD_ECAP_PASID | VTD_ECAP_PSS; + s->ecap = VTD_ECAP_PASID | deposit64(s->ecap, 35, 5, s->pasid - 1); } } -- 2.47.3
