[PATCH v2 05/16] hw/riscv: Ensure bootrom has correct endianess

[Djordje Todorovic]

---
 hw/riscv/boot.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index e5490beda0..dc9f8a7327 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -31,6 +31,7 @@
 #include "system/qtest.h"
 #include "system/kvm.h"
 #include "system/reset.h"
+#include "exec/tswap.h"
 
 #include <libfdt.h>
 
@@ -439,10 +440,24 @@ void riscv_setup_rom_reset_vec(MachineState *machine, 
RISCVHartArrayState *harts
     uint32_t start_addr_hi32 = 0x00000000;
     uint32_t fdt_load_addr_hi32 = 0x00000000;
 
+    start_addr = tswap32(start_addr);
+    fdt_load_addr = tswap32(fdt_load_addr);
+
     if (!riscv_is_32bit(harts)) {
-        start_addr_hi32 = start_addr >> 32;
-        fdt_load_addr_hi32 = fdt_load_addr >> 32;
+        start_addr_hi32 = tswap32(start_addr >> 32);
+        fdt_load_addr_hi32 = tswap32(fdt_load_addr >> 32);
+    
+         if (target_needs_bswap()) {
+            uint32_t temp = start_addr;
+            start_addr = start_addr_hi32;
+            start_addr_hi32 = temp;
+
+            temp = fdt_load_addr;
+            fdt_load_addr = fdt_load_addr_hi32;
+            fdt_load_addr_hi32 = temp;
+        }
     }
+
     /* reset vector */
     uint32_t reset_vec[10] = {
         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-- 
2.34.1