On 2/21/26 2:02 AM, Tao Tang wrote:
The current definition of the SMMU_CR0_RESERVED mask is incorrect.
It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while
treating bit 9 (RES0) as an implemented bit.
According to the SMMU architecture specification, the layout for CR0 is:
| 31:11| RES0 |
| 10 | DPT_WALK_EN |
| 9 | RES0 |
| 8:6 | VMW |
| 5 | RES0 |
| 4 | ATSCHK |
| 3 | CMDQEN |
| 2 | EVENTQEN |
| 1 | PRIQEN |
| 0 | SMMUEN |
Signed-off-by: Tao Tang <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Link: https://lists.gnu.org/archive/html/qemu-arm/2025-06/msg00088.html
---
include/hw/arm/smmuv3-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier <[email protected]>
