On Sat, Feb 21, 2026 at 06:02:20PM +0800, Tao Tang wrote: > The current definition of the SMMU_CR0_RESERVED mask is incorrect. > It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while > treating bit 9 (RES0) as an implemented bit. > > According to the SMMU architecture specification, the layout for CR0 is: > | 31:11| RES0 | > | 10 | DPT_WALK_EN | > | 9 | RES0 | > | 8:6 | VMW | > | 5 | RES0 | > | 4 | ATSCHK | > | 3 | CMDQEN | > | 2 | EVENTQEN | > | 1 | PRIQEN | > | 0 | SMMUEN | > > Signed-off-by: Tao Tang <[email protected]> > Reviewed-by: Eric Auger <[email protected]> > Link: https://lists.gnu.org/archive/html/qemu-arm/2025-06/msg00088.html
I think fixes as this, should be separate, that would make the series smaller. Reviewed-by: Mostafa Saleh <[email protected]> Thanks, Mostafa > --- > include/hw/arm/smmuv3-common.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h > index 67a23fbeaae..2df54ba60f9 100644 > --- a/include/hw/arm/smmuv3-common.h > +++ b/include/hw/arm/smmuv3-common.h > @@ -355,7 +355,7 @@ REG32(CR0, 0x20) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -#define SMMU_CR0_RESERVED 0xFFFFFC20 > +#define SMMU_CR0_RESERVED 0xFFFFFA20 > > REG32(CR0ACK, 0x24) > REG32(CR1, 0x28) > -- > 2.34.1 >
