Hi Pierrick,
On 2026/2/26 05:59, Pierrick Bouvier wrote:
On 2/21/26 2:18 AM, Tao Tang wrote:
Add access control for command queue and event queue related registers
to ensure they can only be modified under proper conditions.
For command queue (CMDQ):
- smmu_cmdq_disabled_stable(): checks CMDQ bit in CR0/CR0ACK
- smmu_cmdq_base_writable(): checks IDR1.QUEUES_PRESET==0 and CMDQ
disabled
For event queue (EVTQ):
- smmu_eventq_disabled_stable(): checks EVTQ bit in CR0/CR0ACK
- smmu_eventq_base_writable():checks IDR1.QUEUES_PRESET==0 and EVTQ
disabled
- smmu_eventq_irq_cfg_writable(): checks MSI support and EVENTQ_IRQEN
state
Additionally, mask reserved bits on writes using
SMMU_QUEUE_BASE_RESERVED
for queue base registers and SMMU_EVENTQ_IRQ_CFG0_RESERVED for
EVENTQ_IRQ_CFG0.
Fixes: fae4be38b35d ("hw/arm/smmuv3: Implement MMIO write operations")
Signed-off-by: Tao Tang <[email protected]>
---
hw/arm/smmuv3.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 154 insertions(+), 3 deletions(-)
It seems like we use the same pattern a lot of time for various SMMU
registers, and makes me wonder if we could not introduce proper
register definitions with callbacks similar to Arm *_reginfo.
That said, it's definitely out of the scope for this series:
Reviewed-by: Pierrick Bouvier <[email protected]>
Thanks for your suggestion. I will consider refactoring it after merging
the current series.
Best regards,
Tao
