On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <[email protected]> wrote:
> Hi > > I was referring this commit of upstream kernel which xilinx added BXRS > register in Cadence UART driver > serial: xuartps: Adds RXBS register support for zynqmp · > torvalds/linux@3816b2f > < > https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889 > > > > Peter Maydell 於 2026/2/16 下午 06:53 寫道: > > CAUTION: This email originated from outside of the organization. Do not > click links or open attachments unless you recognize the sender and know > the content is safe. > > > > > > On Thu, 12 Feb 2026 at 10:47, Kuan-Jui Chiu <[email protected]> wrote: > >> The new CADENCE UART driver in upstream kernel access BXRS register > >> This patch adds BXRS (RX FIFO byte status register) or there would be > >> kernel panic if user are using the new CADENCE UART driver > >> > >> Signed-off-by: Kuan-Jui Chiu <[email protected]> > > Hi; thanks for this patch. > > > >> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > >> index eff6a3c4d1..f57cad57a8 100644 > >> --- a/hw/char/cadence_uart.c > >> +++ b/hw/char/cadence_uart.c > >> @@ -120,6 +120,7 @@ > >> #define R_PMIN (0x3C/4) > >> #define R_PWID (0x40/4) > >> #define R_TTRIG (0x44/4) > >> +#define R_RXBS (0x48/4) > > Where is this register documented? The cadence_uart.c file > > references the Zynq 7000 Soc TRM UG585; its URL for that > > is out of date, but looking at the copy on the AMD website, > > there is a table giving the register summary for the UART: > > > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART > > and it lists only registers from offsets 0 to 0x44. > > > > thanks > > -- PMM > Hi, There's documentation here for zynqmp: https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register I haven't looked to carefully, it may be a register that didn't exist in the version of the UART on zynq and was added in the version of the uart in the zynqmp. Cheers, Edgar
