On Tue, Mar 3, 2026 at 12:44 PM Peter Maydell <[email protected]> wrote:
> On Tue, 3 Mar 2026 at 18:32, Edgar E. Iglesias <[email protected]> > wrote: > > > > > > > > On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <[email protected]> wrote: > >> > >> Hi > >> > >> I was referring this commit of upstream kernel which xilinx added BXRS > >> register in Cadence UART driver > >> serial: xuartps: Adds RXBS register support for zynqmp · > >> torvalds/linux@3816b2f > >> < > https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889 > > > >> > >> Peter Maydell 於 2026/2/16 下午 06:53 寫道: > > >> > Where is this register documented? The cadence_uart.c file > >> > references the Zynq 7000 Soc TRM UG585; its URL for that > >> > is out of date, but looking at the copy on the AMD website, > >> > there is a table giving the register summary for the UART: > >> > > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART > >> > and it lists only registers from offsets 0 to 0x44. > > > There's documentation here for zynqmp: > > > https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register > > > > I haven't looked to carefully, it may be a register that didn't exist in > the version of the UART on zynq and was added in the version of the uart in > the zynqmp. > > Thanks. On the subject of Xilinx specs, do you have an opinion on > https://gitlab.com/qemu-project/qemu/-/issues/3297 ? > Our Xilinx AXI ethernet device model lets software write to > the PHY registers for the PHY ID, and it's not clear to me > whether these registers are supposed to be read-only or not. > > Yes, they should be read-only, there's probably more registers and fields that have the wrong access restrictions as well. The PHY model is super simple, created just to get guests to not get stuck on boot or fail to use the PHY... IIRC, there's been several attempts on list to create a better MDIO/PHY interface with shared PHY models but never got merged. Cheers, Edgar
