On AST2700 platforms, system DRAM is mapped above 4GB with the base address at 0x400000000.
The Linux EHCI driver programs the segment register to zero when 64-bit addressing is supported. As a result, descriptor addresses derived from the EHCI registers do not include the DRAM base address. Descriptor memory is allocated through the DMA API with a 64-bit DMA mask, which allows descriptors to be placed in DRAM above 4GB. When running on AST2700, this means EHCI queue heads (QH) and queue element transfer descriptors (qTD) reside at addresses starting from 0x400000000. Set the descriptor-addr-offset property to the DRAM base so the emulated EHCI controller can construct the correct descriptor addresses when accessing system memory. Signed-off-by: Jamin Lin <[email protected]> --- hw/arm/aspeed_ast27x0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 4a1f7cad73..3cdbf78ac1 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -858,6 +858,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) for (i = 0; i < sc->ehcis_num; i++) { object_property_set_bool(OBJECT(&s->ehci[i]), "caps-64bit-addr", true, &error_abort); + object_property_set_int(OBJECT(&s->ehci[i]), "descriptor-addr-offset", + sc->memmap[ASPEED_DEV_SDRAM], + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { return; } -- 2.43.0
