The EHCI CTRLDSSEGMENT register provides the upper 32 bits [63:32] used to form 64-bit addresses for EHCI control data structures. Per EHCI 1.0 spec section 2.3.5, when the HCCPARAMS 64-bit Addressing Capability bit is zero, CTRLDSSEGMENT is not used: software cannot write it and reads must return zero.
Add a capability check in the operational register write handler and reject guest writes to CTRLDSSEGMENT when 64-bit addressing is not enabled. Signed-off-by: Jamin Lin <[email protected]> --- hw/usb/hcd-ehci.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 9e82328116..d7a0917caf 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1106,7 +1106,14 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, " is enabled and HC is enabled\n"); } break; - + case CTRLDSSEGMENT: + if (!s->caps_64bit_addr) { + fprintf(stderr, + "ehci: write to CTRLDSSEGMENT while " + "64-bit addressing capability is disabled\n"); + return; + } + break; case ASYNCLISTADDR: if (ehci_async_enabled(s)) { fprintf(stderr, -- 2.43.0
